• The KIPS Transactions:PartC
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• v.10C no.2
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• pp.185-190
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• 2003

Bluetooth communication is based on piconet, which is composed by one master and maximum seven slaves. Several piconets can be interconnected via an inter-piconet Bluetooth unit called a bridge unit to form a Bluetooth scatternet. This bridge node can make its presence in each piconet by switching. This switching must be carefully scheduled so that slot wastage and, hence, packet delays are minimized. In this paper, we introduce an efficient inter-piconet scheduling scheme based on sniff mode. This scheme tries to minimize the wastage of slots by having the bridge unit sniff with its peering masters with time limits and communicate with its slaves in remaining slots. The sniff time limits are determined adaptively based on the amount of traffic in each piconet. Simulation results show this scheme outperforms round-robin scheme based on sniff intervals of equal lengths.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.15 no.11
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• pp.2433-2438
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• 2011

Bus system consists of several masters, slaves, arbiter and decoder in a bus. Master means the processor that performs data command like CPU, DMA, DSP and slave means the memory that responds the data command like SRAM, SDRAM and register. Furthermore, as multiple masters can't use a bus concurrently, arbiter plays an role in bus arbitration. In compliance with the selection of arbitration method, bus system performance can be changed definitely. Fixed priority and round-robin are used in general arbitration method and TDMA and Lottery bus methods are proposed currently as the improved arbitration schemes. In this study, we proposed the score arbitration method and synthesized it using Hynix 0.18um technology, after design of RTL. Also we analyze the performance compared with general arbitration methods through simulation.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.42 no.4 s.334
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• pp.9-18
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• 2005

This paper proposes the novel synchronous segmented bus architecture that has the pipeline bus architecture based on OCP(open core protocol) and the memory-oriented bus for MPEG system. The proposed architecture has bus architectures that support the memory interface for image data processing of MPEG system. Also it has the segmented hi-directional multiple bus architecture for multitasking processing by using multi -masters/multi - slave. In the scheme address of masters and slaves are fixed so that they are arranged for the location of IP cores according to operational characteristics of the system for efficient data processing. Also the bus architecture adopts synchronous segmented bus architecture for reuse of IP's and architecture or developed chips. This feature is suitable to the high performance and low power multimedia SoC systum by inherent characteristics of multitasking operation and segmented bus. Proposed bus architecture can have up to 3.7 times improvement in the effective bandwidth md up to 4 times reduction in the communication latency.

• Journal of the Korea Academia-Industrial cooperation Society
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• v.13 no.9
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• pp.3876-3881
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• 2012

In typical master/slave teleoperation systems, a human operator generally manipulates the master to control the slave through the visual information like camera image. However, the operator may get into trouble due to the limited visual information depending on the camera positions and the delay on the visual information because of low communication bandwidth. To cope with this inherit problem in the camera-based teleoperation system, this paper presents a teleoperation system using a reconstructed graphic model instead of the camera image. The proposed teleoperation system consists of a robot control module, a master module using a force-reflective joystick, and a graphic user interface (GUI) module. The graphic user interface module provides the operator with a 3D model reconstructed using a small set of sensing data received from the remote site. The proposed teleoperation system is evaluated through a peg-in-hole assembly task.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.46 no.2
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• pp.38-44
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• 2009

Bus system consists of several masters, slaves, arbiter and decoder in a bus. Master means the processor that performs data command like CPU, DMA, DSP and slave means the memory that responds the data command like SRAM, SDRAM and register. Furthermore, as multiple masters can't use a bus concurrently, arbiter plays an role in bus arbitration. In compliance with the selection of arbitration method bus system performance can be charged definitely. Fixed priority and round-robin are used in general arbitration method and TDMA and Lottery bus methods are proposed currently as the improved arbitration schemes. In this stuff, we proposed the score arbitration method and composed TLM algorithm. Also we analyze the performance compared with general arbitration methods through simulation. In the future, bus arbitration policy will be developed with the basis of the score arbitration method and improve the performance of bus system.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.47 no.1
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• pp.69-78
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• 2010

To implement the high performance SoC, we propose the flying master bus architecture that a specially defined master named as the flying master directly accesses the selected slaves with no regard to the bus protocol. The proposed bus architecture was implemented through Verilog and mapped the design into Hynix 0.18um technology. As master and slave wrappers have around 150 logic gate counts, the area overhead is still small considering the typical area of modules in SoC designs. In TLM performance simulation about proposed architecture, 25~40% of transaction cycle and 43~60% of bus efficiency are increased and 43~77% of request cycle is decreased, compared with conventional bus architecture. Conclusively, we assume that the proposed flying master bus architecture is promising as the leading candidate of the bus architecture in the aspect of performance and efficiency.

• Journal of Advanced Marine Engineering and Technology
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• v.38 no.3
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• pp.292-301
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• 2014

This paper describes development of distributed type independent electro-hydraulic ballast valve remote control system with diagnostic function based on fuzzy inference using redundant Modbus communication and ethernet Modbus TCP/IP. Diagnostic function estimate degradation of system components and diagnose system faults, which results in shortage of fault maintenance time and improvement of system safety. Slave devices which control each valve and master device which command, monitor and diagnose slave system are developed. Slave devices are connected to master device with redundant Modbus networks and master device is connected to ship's integrated control system with Modbus TCP/IP. Also this paper describes development of simulator to test and confirm whether developed system can be integrated with ship's integrated control and monitoring system.

• The Transactions of the Korean Institute of Power Electronics
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• v.5 no.2
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• pp.184-191
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• 2000

We discussed load CUlTent sharing for Master/Slave convertedMSC) type two DC-DC Converters parallel operation using a single current sensor method. In the conventional method, two CTs have been used to share t the load CUlTent equally with two coηverters‘ This paper presents a novel load CUlTent distribution method u using a single CUlTent sensor that can share load CUlTent effectively with only one CT in the Master-Slave C conveη:ers(MSCs) type. To confirm parallel operational performance of proposed DC-DC converters parallel operation, two experimental prototype converters were designed, implemented and experimented under three a arbitrary conditions. A load cur‘rent shahring perforrnance of the proposed method was compared with that of a c conventional peak CUt${\gamma}$ent method requmng two CTs. Those experimental results show that load cUlTent s sharing performance of paralleled two converters using a single CUlTent sensor was good and operated as well a as conventional method (ex, Pe밟 CUlTent Method)

• Proceedings of the Korean Radioactive Waste Society Conference
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• 2003.11a
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• pp.388-394
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• 2003

To handle the high level radioactive materials such a spent fuel, the master-slave manipulators (MSM) are widely used as a remote handling device in nuclear facilities such as the hot cell with sealed and shielded space. In this paper, the Digital Mockup which simulates the remote operation of the Advanced Conditioning Process(ACP) is developed. Also, the workspace and the motion of the slave manipulator, as well as, the remote operation task should be analyzed. The process equipment of ACP and Maintenance/Handling Device are drawn in 3D CAD models using IGRIP. Modeling device of manipulator is assigned with various mobile attributes such as a relative position, kinematics constraints, and a range of mobility, The 3D graphic simulator using the external input device of space ball displays the movement of manipulator. To connect the external input device to the graphic simulator, the interface program of external input device with 6 DOF is deigned using the Low Level Tele-operation Interface(LLTI). The experimental result shows that the developed simulation system gives much-improved human interface characteristics and shows satisfactory response characteristics in terms of synchronization speed. This should be useful for the development of work's education system in the virtual environment.

• Journal of KIISE:Information Networking
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• v.32 no.6
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• pp.668-675
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• 2005

With the proliferation of wireless network and the advances of the embedded systems, the traditional distributed systems begin to include the wireless embedded systems. Clock synchronization in the distributed systems is one of the major issues that should be considered for diverse Purposes including synchronization, ordering, and consistency. Many clock synchronization algorithms have been proposed over the years. Since clock synchronization in wireless embedded systems should consider the low bandwidth of a network and the poor resources of a system, most traditional algorithms cannot be applied directly. We propose a clock synchronization algorithm in wireless embedded systems, extending IEEE 802.11 standard. The proposed algorithm can not only achieve high precision by loosening constraints and utilizing the characteristics of wireless broadcast but also provide continuous time synchronization by tolerating the message losses. In master/slave structure the master broadcasts the time information and the stave computes the clock skew and the drift to estimate the synchronized time of the master. The experiment results show that the achieved standard deviation by the Proposed scheme is within the bound of about 200 microseconds.