• Journal of the Korean Institute of Telematics and Electronics C
• /
• v.36C no.3
• /
• pp.17-25
• /
• 1999

This paper proposes a new bit-serial multiplier/divider architecture to reduce the hardware complexity significantly and to maintain the same number of cycles compared with existing architectures. Since the proposed bit-serial multiplier/divider architecture does not extend the number of bits in registers and an adde $r_tractor to calculate a partial product or a partial remainder, the hardware overhead can be greatly reduced. In addition, the proposed architecture can perform an additio $n_traction and a shift operation in parallel and the number of cycles for $\textit{N}$-bit multiplication and division for the proposed circuits is $\textit{N}$ and $\textit{N}$ + 2, repectively. Thus, the number of cycles for multiplication and division is the same compared with existing architectures. The SliM Image Processor employs the proposed multiplier/divider architecture and proves the performance of the proposed architecture.cture.

• Proceedings of the Korean Society of Broadcast Engineers Conference
• /
• 2008.02a
• /
• pp.89-93
• /
• 2008

본 논문에서는 단순전력 분석(SPA)과 오류주입공격(FA)에 안전한 중국인의 나머지 정리를 이용한 RSA 암호 시스템(CRT-RSA)에 대하여 논한다. CRT-RSA를 이용한 서명 알고리즘은 스마트카드와 같은 내장형 장치(embedded device)에서 널리 사용된다. 하지만 이러한 장치들은 전력분석 공격과 오류주입 공격에 취약하다. 2005년 Giraud가 처음으로 단순전력분석과 오류주입공격에 모두 안전한 대응 방법을 제안하였다. 본 논문에서는 Giraud의 대응 방법에 대한 다른 공격방법을 소개하고, 제시한 공격 방법에도 안전한 대응 방법을 제안한다. 본 논문에서 제안하는 대응 방법은 세 개의 메모리와 덧셈과 뺄셈연산을 추가적으로 요구한다. 추가적으로 요구되는 연산량은 모듈러 지수승 연산에 필요한 연산량에 비교하면 크게 고려하지 않아도 될 연산량이다. 그러므로 본 논문에서 제안하는 대응 방법은 내장형 장치와 같은 환경에서 안전하고 효율적으로 이용될 수 있다.

• The Mathematical Education
• /
• v.51 no.1
• /
• pp.21-45
• /
• 2012

The purpose of the study was to investigate how students understand each operations with whole numbers and fractions, and the relationship between their knowledge of operations with whole numbers and conceptual understanding of operations on fractions. Researchers categorized students' understanding of operations with whole numbers and fractions based on their semantic structure of these operations, and analyzed the relationship between students' understanding of operations with whole numbers and fractions. As the results, some students who understood multiplications with whole numbers as only situations of "equal groups" did not properly conceptualize multiplications of fractions as they interpreted wrongly multiplying two fractions as adding two fractions. On the other hand, some students who understood multiplications with whole numbers as situations of "multiplicative comparison" appropriately conceptualize multiplications of fractions. They naturally constructed knowledge of fractions as they build on their prior knowledge of whole numbers compared to other students. In the case of division, we found that some students who understood divisions with whole numbers as only situations of "sharing" had difficulty in constructing division knowledge of fractions from previous division knowledge of whole numbers.

• The Journal of the Institute of Internet, Broadcasting and Communication
• /
• v.20 no.2
• /
• pp.187-193
• /
• 2020

Floating point arithmetic in microprocessor is the computation of addition, subtraction, multiplication, and division of floating point data to improve accuracy. In general, when designing a processor, floating point instructions are often excluded because of its complexity and only integer instructions are provided. However, in order to carry out the computations for not only engineering and technical operations but also artificial intelligence and neural networks that are in the spotlight today, floating point operations must be included. In this paper, we design a 32-bit ARMv4 family of processors with floating-point arithmetic instructions using VHDL and verify with ModelSim. As a result, ARM's floating point instructions are successfully executed.

• Proceedings of the IEEK Conference
• /
• 1999.06a
• /
• pp.345-348
• /
• 1999

본 논문에서는 내장형 응용에 적합한 RISC 마이크로프로세서와 DSP 프로세서의 기능을 유기적으로 결합한 구조를 연구하고 이를 설계한다. 프로그램의 크기를 줄이기 위해 RISC 명령어는 16비트 명령어 집합을 설계하고 분기 명령어로 인한 손실을 줄이기 위해 한 개의 지연 슬롯을 갖고 있다. DSP 명령어는 32비트 길이를 갖고 한 명령어로 곱셈, 덧셈(뺄셈), 두 가지 데이터 이동을 할 수 있어서 한 사이클에 최대 네 가지 동작을 할 수 있다 파이프라인 단계는 IF, ID, EX, MA, WB/DSP의 다섯 단계로 구성된다. DSP 기능을 지원하기 위해 내부 루프 버퍼를 갖고 정수 실행부에서는 주소 발생을 위한 전용 하드웨어와 DSP 유닛에서는 곱셈 및 누적 기능을 지원하기 위한 17 × 17 비트 곱셈기가 내장된다. 제안된 구조의 설계는 Verilog-HDL을 이용하여 top-down 설계 방식으로 설계되었고 각 기능 검증을 마친 후 3.3V, 0.6㎛ CMOS triple metal single poly 공정을 이용하여 합성하고 레이아웃 하였다.

• The Journal of the Korea Contents Association
• /
• v.10 no.3
• /
• pp.1-9
• /
• 2010

In this paper, we propose a new method of improving accuracy of motion estimation in mobile environments, compared with Rosten's algorithm. The present method selects corners as feature points. The Rosten's algorithm uses simple addition and subtraction to detect the corners. Although it has the advantage of faster processing speed, Rosten's algorithm has a drawback of low performance in motion estimation. We use the NCC(Normalized Cross Correlation) coefficients to match the corners, and remove in two steps the outliers of inaccurate matching corners. We compare the proposed algorithm with Rosten's algorithm by applying both to the real images. We find that the proposed method shows better performance than Rosten's algorithm in motion estimation. In addition, we implement the present method on mobile devices and confirm that it works in mobile environments in real time.

• The Journal of Korean Institute of Communications and Information Sciences
• /
• v.34 no.3C
• /
• pp.322-328
• /
• 2009

This paper proposes new simplified sum-product (SSP) decoding algorithm to improve BER performance for low-density parity-check codes. The proposed SSP algorithm can replace multiplications and divisions with additions and subtractions without extra computations. In addition, the proposed SSP algorithm can simplify both the In[tanh(x)] and tanh-1 [exp(x)] by using two quantization tables which can reduce tremendous computational complexity. Moreover, the simulation results show that the proposed SSP algorithm can improve about $0.3\;{\sim}\;0.8\;dB$ of BER performance compared with the existing modified sum-product algorithms.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
• /
• 2010.05a
• /
• pp.809-811
• /
• 2010

In most floating-point operations related with 3D graphic applications for mobile devices, properly approximated data calculations with reduced complexity and low power are preferable to exactly rounded floating-point operations with unnecessary preciseness with cost. Among all the sophisticated floating-point arithmetic operations, multiplication and division are the most complicated and time-consuming, and they can be transformed into addition and subtraction repectively by adopting the logarithmic conversion. In this process, the most important factor for performance is how high we can make an approximation of the logarithm conversion. In this paper, we cover the trends in studying the logarithm conversion circuit designs. We also discuss the important factor in design issues and the applicable fields in detail.

• The Transactions of the Korea Information Processing Society
• /
• v.4 no.11
• /
• pp.2861-2873
• /
• 1997

An FPU(Floating Point unit) is the principle component in high performance computer and is placed on a chip together with main processing unit recently. As a Processing speed of the FPU is accelerated, the rounding stage, which occupies one of the floating point Processing steps for floating point operations, has a considerable effect on overall floating point operations. In this paper, by studying and analyzing the processing flows of the conventional floating point adder/subtractor, multipler and divider, which are main component of the FPU, efficient rounding mechanisms are presented. Proposed mechanisms do not require any additional execution time and any high speed adder for rounding operation. Thus, performance improvement and cost-effective design can be achieved by this approach.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
• /
• 2009.05a
• /
• pp.690-692
• /
• 2009

PLL은 위상주파수검출기(PFD), 차지펌프(Charge Pump), 루프필터(Loop Filter), 전압제어발진기(VCO), Divider로 구성하고 있는데 본 논문에서는 설계된 차지펌프 PLL을 시뮬레이션을 해보고 그 결과를 정리하고 레이아웃(layout)까지 하였다. 차지펌프 설계에 있어서 전류 부정합, 전하 공유, 전하주입, 누설 전류등을 고려할 필요가 있다. 설계된 차지펌프는 전류 부정합을 감소시키기 위해 전류뺄셈회로를 이용하여 전류 부정합을 감소시켰으며, spurs를 억제할 수 있도록 설계되였다. 설계된 회로는 $0.18{\mu}m$ CMOS 공정 기술을 사용하여 CADENCE사의 specter로 시뮬레이션 하였으며, virtuso2로 레이아웃 하였다.