• Journal of the Institute of Electronics Engineers of Korea SD
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• v.44 no.7 s.361
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• pp.45-53
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• 2007

In this paper, we propose an efficient hardware architecture for H.264/AVC CAVLC (Context-based Adaptive Variable Length Coding) encoding. Previous CAVLC architectures search all of the coefficients to find statistic characteristics in a block. However, it is unnecessary information that zero coefficients following the last position of a non-zero coefficient when CAVLC encodes residual coefficients. In order to reduce this unnecessary operation, we propose two techniques, which detect the first and last position of non-zero coefficients and arrange non-zero coefficients sequentially. By adopting these two techniques, the required processing time was reduced about 23% compared with previous architecture. It was designed in a hardware description language and total logic gate count is 16.3k using 0.18um standard cell library Simulation results show that our design is capable of real-time processing for $1920{\times}1088\;30fps$ videos at 81MHz.

• Journal of the Institute of Convergence Signal Processing
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• v.5 no.3
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• pp.230-235
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• 2004

This paper describes FPGA implementation of a pointer interpreter which can support a synchronization of SDH(or SONET)-based transmission network. The pointer interpreter consists of a pointer-word extractor and a pointer-word interpreter The pointer-word extractor which is composed of mod-6480 counter, shift register and pointer synchronizing block, finds out the H1 and H2 pointer word from a 51.84 Mb/s AU-3/STS-1 data frame and then performs the synchronizing with a 6.48 Mb/s by dividing them in 8. Based on the extracted pointer word, pointer-word interpreter analyzes pointer states such LOP, AIS and NORM according to pointer state-transition algorithm. It consists of a majority vote, a pointer word valid/invalid check, a pointer justification, and a pointer state check. The simulation results of Xilinx Virtex XCV200PQ240 FPGA chip shows the exact pointer word extraction and correct decision of pointer status based on extracted pointer word. The proposed pointer interpreter is suitable for pointer interpretation of 155 Mb/s STM-1/STS-3 frame.

• The Transactions of the Korea Information Processing Society
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• v.6 no.9
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• pp.2294-2304
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• 1999

Our research purpose in this paper is to improve the performance of query processing in GIS(Geographic Information System) by enhancing the I/O performance exploiting parallel I/O and efficient disk access. By packing adjacent spatial data, which are very likely to be referenced concurrently, into one block or continuous disk blocks, the number of disk accesses and the disk access overhead for query processing can be decreased, and this eventually leads to the I/O time decrease. So, in this paper, we proposes EPR(Enhanced Parallel R-tree) indexing method which integrates the parallel I/O method of the previous Parallel R-tree method and a packing-based clustering method. The major characteristics of EPR method are as follows. First, EPR method arranges spatial data in the increasing order of proximity by using Hilbert space filling curve, and builds a packed R-tree by bottom-up manner. Second, with packing-based clustering in which arranged spatial data are clustered into continuous disk blocks, EPR method generates spatial data clusters. Third, EPR method distributes EPR index nodes and spatial data clusters on multiple disks through round-robin striping. Experimental results show that EPR method achieves up to 30% or more gains over PR method in query processing speed. In particular, the larger the size of disk blocks is and the smaller the size of spatial data objects is, the better the performance of query processing by EPR method is.

• KIPS Transactions on Computer and Communication Systems
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• v.10 no.8
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• pp.223-230
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• 2021

The lightweight block cipher PIPO announced at ICISC'20 has been effectively implemented by applying the bit slice technique. In this paper, we propose a parallel optimal implementation of PIPO for ARM processors. The proposed implementation enables parallel encryption of 8-plaintexts and 16-plaintexts. The implementation targets the A10x fusion processor. On the target processor, the existing reference PIPO code has performance of 34.6 cpb and 44.7 cpb in 64/128 and 64/256 standards. Among the proposed methods, the general implementation has a performance of 12.0 cpb and 15.6 cpb in the 8-plaintexts 64/128 and 64/256 standards, and 6.3 cpb and 8.1 cpb in the 16-plaintexts 64/128 and 64/256 standards. Compared to the existing reference code implementation, the 8-plaintexts parallel implementation for each standard has about 65.3%, 66.4%, and the 16-plaintexts parallel implementation, about 81.8%, and 82.1% better performance. The register minimum alignment implementation shows performance of 8.2 cpb and 10.2 cpb in the 8-plaintexts 64/128 and 64/256 specifications, and 3.9 cpb and 4.8 cpb in the 16-plaintexts 64/128 and 64/256 specifications. Compared to the existing reference code implementation, the 8-plaintexts parallel implementation has improved performance by about 76.3% and 77.2%, and the 16-plaintext parallel implementation is about 88.7% and 89.3% higher for each standard.

• Journal of the Institute of Electronics Engineers of Korea SP
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• v.46 no.5
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• pp.66-79
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• 2009

In this paper, we propose a new adaptive intra coding technique using 1-D and 2-D integer transforms for improving coding efficiency of H.264/AVC. Proposed technique selects the most effective transform and prediction mode for each block after processing 1-D and 2-D transforms of all prediction modes. In case of using 1-D transform, $4{\times}4$ block is divided into four $1{\times}4$ or $4{\times}1$ subblocks and then each subblock is predicted and subtracted by using the decoded subblock located at the nearest position in the direction of prediction. After prediction error subblock is processed by 1-D transform and quantization, four subblocks are merged back into original $4{\times}4$ block and then, reordered as 1-D signal by a DC biased zigzag scanning pattern according to the prediction mode. Finally, comparing the coding efficiency between bitstreams based on 1-D transform and conventional 2-D transform, prediction mode and quantized coefficients for each block are decided and corresponding quantized coefficients are transmitted. Experimental results show that the proposed adaptive technique increases 0.34dB in BD-PSNR and decreases 4.03% in BD-Bitrate on the average compared with H.264/AVC.

• Proceedings of the Korea Information Processing Society Conference
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• 2006.11a
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• pp.333-336
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• 2006

플래시 메모리는 휴대폰과 PDA 와 같은 이동 기기에서 저장 장치로 널리 사용되고 있다. 또한 기가바이트(GB) 단위의 대용량화로 인해 노트북과 개인용 컴퓨터에서 보조기억장치로 사용되고 있다. 요즘에는 대용량의 데이터를 효율적으로 다루기 위한 B+트리와 같은 자료구조를 플래시 메모리상에서 저비용의로 구현하려는 연구들이 이루어지고 있다. 지금까지의 연구에서는 플래시 메모리에서 B+트리를 구축할 때 노드 크기를 플래시 메모리의 섹터(sector) 크기로 사용해왔다. 본 논문에서는 노드 크기가 플래시 메모리의 섹터 크기보다 더 커졌을 경우, 플래시 메모리에서 구현되는 B+트리의 구축성능과 검색성능 그리고 저장 공간 사용량을 비교 분석한다. 키 삽입 시 정렬 알고리즘과 비정렬 알고리즘을 각각 사용해 구축비용을 측정하였으며 효율적인 노드 검색을 위해 인덱스 노드 헤드 구조를 사용한다. 그리고 이러한 실험결과는 B+트리 노드 크기를 섹터 크기보다 블록 크기로 할당할 때 B+트리 성능의 우수성을 보인다.

• Journal of the Korea Institute of Information Security & Cryptology
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• v.28 no.3
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• pp.545-550
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• 2018

Ultra-lightweight block cipher CHAM, consisting of simple addition, rotation, and eXclusive-or operations, enables the efficient implementations over both low-end and high-end Internet of Things (IoT) platforms. In particular, the CHAM block cipher targets the enhanced computational performance for the low-end IoT platforms. In this paper, we introduce the efficient implementation techniques to minimize the memory consumption and optimize the execution timing over 8-bit AVR IoT platforms. To achieve the higher performance, we exploit the partly iterated expression and arrange the memory alignment. Furthermore, we exploit the optimal number of register and data update. Finally, we achieve the high RANK parameters including 29.9, 18.0, and 13.4 for CHAM 64/128, 128/128, and 128/256, respectively. These are the best implementation results in existing block ciphers.

• Journal of the Society of Naval Architects of Korea
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• v.38 no.2
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• pp.79-86
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• 2001

This study shows an attempt to generate an assembly sequence and its model for a ship block assembly using the graph theory and graph algorithms. To generate the ship block assembly, we propose four levels of the ship block assembly model such as "geometry mode1", "relational model", "sequential mode1", and "hierarchical model". To obtain the relational model, we used surface and surface intersection algorithm. The sequential model that represents a possible assembly sequence is made by using several graph algorithms from the relational model. The hierarchical model will be constructed from the sequential model in order to represent the block assembly tree and so forth. The purpose of the hierarchical model is to define an assembly tree and to generate the Bill Of Material(BOM). Lastly, the validity of the method proposed in this study is examined with application to ship block assembly models of a single type and double type according to four models mentioned above.

• Journal of KIISE
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• v.43 no.6
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• pp.627-635
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• 2016

When many processes issue write operations alternately on Log-structured File System (LFS), the created files can be fragmented on the file system layer although LFS sequentially allocates new blocks of each process. Unfortunately, this file fragmentation degrades read performance because it increases the number of block I/Os. Additionally, read-ahead operations which increase the number of data to request at a time exacerbates the performance degradation. In this paper, we suggest a new cleaning method on LFS that minimizes file fragmentation. During a cleaning process of LFS, our method sorts valid data blocks by inode numbers before copying the valid blocks to a new segment. This sorting re-locates fragmented blocks contiguously. Our cleaning method experimentally eliminates 60% of file fragmentation as compared to file fragmentation before cleaning. Consequently, our cleaning method improves sequential read throughput by 21% when read-ahead is applied.

• Proceedings of the Korea Information Processing Society Conference
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• 2021.11a
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• pp.201-204
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• 2021

PIPO 경량 블록암호는 ICISC'20에서 발표된 암호이다. 본 논문에서는 PIPO의 단일 평문 최적화 구현과 4평문 병렬 구현을 제안한다. 단일 평문 최적화 구현은 Rlayer의 최적화와 키스케쥴을 포함하지 않은 구현을 진행하였다. 결과적으로 키스케쥴을 포함하는 기존 연구 대비 70%의 성능 향상을 확인하였다. 4평문의 경우 32-bit 레지스터를 최대한 활용하여, 레지스터 내부 정렬과 Rlayer의 최적화 구현을 진행하였다. 또한 Addroundkey 구현에서 메모리 최적화 구현과 속도 최적화 구현을 나누어 구현하였다. 메모리 사용을 줄인 메모리 최적화 구현은 단일 평문 구현 대비 80%의 성능 향상을 확인하였고, 암호화 속도를 빠르게 구현한 속도 최적화 구현은 단일 평문 구현 대비 157%의 성능 향상을 확인하였다.