• The Journal of the Korea institute of electronic communication sciences
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• v.12 no.2
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• pp.345-352
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• 2017

In this paper, we design and implement an educational robot system that can use scratch education with the function of user demanding to perform robot education in actual school site in an embedded environment. It is developed to enable physical education for sensing information processing, software design and programming practice training that is the basis of robotic system. The development environment of the system is Arduino Uno based product using Atmega 328 core, debugging environment based on Arduino Sketch, firmware development language using C language, OS using Windows, Linux, Mac OS X. The system operation process receives the control command of the server using the Bluetooth communication, and drives various sensors of the educational robot. The curriculum includes Scratch program and Bluetooth communication, which enables real-time scratch training. It also provides smartphone apps and is designed to enable education like C and Python through expansion. Teachers at the school site used the developed products and presented performance processing results satisfying the missionary needs of the missionaries.

• The KIPS Transactions:PartA
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• v.13A no.4 s.101
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• pp.295-304
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• 2006

Java has been established as one of the most widely-used languages owing to its support of object-oriented concepts, safety, and flexibility. Garbage collection in the Java virtual machine is a core component that relieves application programmers of difficulties related to memory management. In this paper, we propose a memory manager and a garbage collector that is implemented on a embedded java virtual machine. The memory manager divide a heap into various-sized cells and manages it as blocks of same-sized cells. So it is possible to allocate and free memory fast. We adopted the 3-color based Mark & Sweep garbage collector as our base algorithm and we propose 4-color based Mark & Sweep garbage collector for supporting multi-threaded program. The proposed garbage collector occurs memory fragmentation but we show through a experiment that the fragmentation ratio is almost fixed according as we create objects continuously.

• Journal of Korea Multimedia Society
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• v.14 no.8
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• pp.981-991
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• 2011

MIP(Maximum Intensity Projection) is a volume rendering technique which is essential for the medical imaging system. MIP rendering based on the ray casting method produces high quality images but takes a long time. Our aim is improvement of the rendering speed using GPGPU(General-purpose computing on Graphic Process Unit) technique. In this paper, we present the ray casting algorithm based on CUDA(an acronym for Compute Unified Device Architecture) which is a programming language for GPGPU and we suggest new acceleration methods for CUDA. In detail, we propose the block based space leaping which skips unnecessary regions of volume data for CUDA, the bisection method which is a fast method to find a block edge, and the initial value estimation method which improves the probability of space leaping. Due to the proposed methods, we noticeably improve the rendering speed without image quality degradation.

• Journal of Digital Contents Society
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• v.9 no.3
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• pp.371-377
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• 2008

Recently the performance of GPU is increasing much faster compared to GPU and GPU is used for various application programs. In this paper, MPEG-2 Decoder is implemented based on a GPU programming language, CG. The proposed methodology is to perform block rendering with texture data according to video standard with very high parallelism by using the pipeline of GPU which is a stream processing structure. To reduce the data bandwidth between system memory and GPU, local memory is used for graphic card. According to the experiment, the proposed scheme shows performance improvement by more than 2 times compared to CPU based scheme.

• Journal of KIISE:Software and Applications
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• v.35 no.3
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• pp.149-161
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• 2008

As Programmable Logic Controllers(PLCs) are frequently used to implement real-time safety critical software, testing of PLC software is getting more important. We propose a structural testing technique on Function Block Diagram(FBD) which is one of the PLC programming languages. In order to test FBD networks, we define templates for function blocks including timer function blocks and propose an algorithm based on the templates to transform a unit FBD into a flowgraph. We generate test cases by applying existing testing techniques to the generated flowgraph. While the existing FBD testing technique do not consider infernal structure of FBD to generate test cases and can be applied only to FBD from which the specific intermediate model can be generated, this approach has advantages of systematic test case generation considering infernal structure of FBD and applicability to any FBD without regard to its intermediate format. Especially, the proposed method enables FBD networks including timer function blocks to be tested thoroughly. To demonstrate the effectiveness of the proposed method, we use trip logic of bistable processor of digital nuclear power plant protection systems which is being developed in Korea.