• 주택과사람들
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• s.192
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• pp.94-99
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• 2006

프랑스 남부 지중해변에 위치한 세계적 휴양 도시 칸(Cannes)은 매년 각종 박람회와 축제들로 분주하다. 흔히 알고 있는 것처럼 칸에서 영화제만 열리는 것이 아니기 때문이다. 올 부동산 투자박람회 미핌(MIPIM)을 통해 세계 부동산의 개발 트렌드와 현주소를 조명해보자.

• The Korean Publising Journal, Monthly
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• s.231
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• pp.6-7
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• 1998

해외시장 개척에 나선 출판사들의 움직임이 분주하다 한국의 정신문화를 알리는 차원에서 벗어나 실리를 위해 뛰고 있는 것이다. 출판물 수출에 대한 전망은 밝은 편이며, 국내 출판시장에 활력을 불어넣어 줄 것으로 기대된다.

• Digital Contents
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• no.4 s.95
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• pp.56-57
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• 2001

콘텐츠 유료화 및 수익모델 찾기는 비단 우리나라만의 이야기는 아니다. 미국도 콘텐츠의 수익모델을 찾기 위한 움직임이 분주하다. 외국의 일부 웹사이트의 수익 모델로 가기 위한 사이트 운용과 수익모델의 방법을 찾아보기 위해 본 기사를 올린다.

• Venture DIGEST
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• s.41
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• pp.6-7
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• 2004

원숭이는 동물 가운데 가장 영리하고 재주있는 동물이라고들 한다. 시시각각 변하는 시대의 물결을 타고 능동적이고 민첩하게 대처해야 하는 벤처인들에게 원숭이의 영특한 호기심과 분주한 활동성은 더 없이 어울린다. 2004년 갑신년 원숭이띠만 특별한 기질을 타고난 원숭이띠 벤처인들을 찾아 만나본다.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.17 no.8 s.111
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• pp.732-738
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• 2006

Divide-by-2 and divide-by-4 circuits which can operate up to 10 GHz are designed. A design method used in these circuits is the TSPC(True Single Phase Clocking) topology. The structure of the TSPC dividers is very simple because they need only a single clock and purely consist of smalt sized cmos devices. Through measurements, we find the fact that in proportion to the bias voltage, the free running frequency increases and the operation region also moves toward a higher frequency region. For operating conditions of bias voltage $3.0{\sim}4.0V$, input power 16dBm and dcoffset $1.5{\sim}2.0V$, 5 GHz and 2.5 GHz output signals divided by 2 and 4 are measured. The layout size of the divide-by-2 circuit is about $500{\times}500 um^2$($50{\times}40um^2$ except pad interconnection part).

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.22 no.5
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• pp.522-527
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• 2011

In this work, a 54 GHz divide-by-3 injection-locked frequency divider(ILFD) based on ring oscillator has been developed in a 0.13-${\mu}M$ Si RFCMOS technology for phase-locked loop(PLL) application. The free-running frequency is 18.92~19.31 GHz with tuning range of 0~1.8 V, consuming 70 mW with a 1.8 V supply voltage. At 0 dBm input power, the locking range is 1.02 GHz(54.82~55.84 GHz) and, with varactor tuning of 0~1.8 V, the total operating range is 2.4 GHz(54.82~57.17 GHz). The fabricated circuit size is 0.42 mm${\times}$0.6 mm including probing pads and 0.099 mm${\times}$0.056 mm for core area.

• Journal of IKEEE
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• v.23 no.3
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• pp.800-804
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• 2019

This paper presents a dual-loop sub-sampling digital PLL for a 2.4 GHz IoT applications. The PLL initially performs a divider-based coarse lock and switches to a divider-less fine sub-sampling lock. It achieves a low in-band phase noise performance by enabling the use of a high resolution time-to-digital converter (TDC) and a digital-to-time converter (DTC) in a selected timing range. To remove the difference between the phase offsets of the coarse and fine loops, a phase offset calibration scheme is proposed. The phase offset of the fine loop is estimated during the coarse lock and reflected in the coarse lock process, resulting in a smooth transition to the fine lock with a stable fast settling. The proposed digital PLL is designed by SystemVerilog modeling and Verilog-HDL and fully verified with simulations.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.17 no.10
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• pp.2409-2418
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• 2013

Two frequency synthesizers are proposed to generate a clock for a sub-sampler of an on-chip oscilloscope in this paper. These proposed frequency synthesizers are designed by using a multi-phase delayed-locked loop (DLL)-based phase selector and a fractional-N phase-locked loop (PLL), and they are analyzed by comparing simulation results of each frequency synthesizer. Two proposed frequency synthesizers are designed using a 65-nm CMOS process with a 1V supply and output the clock with the frequency of 121.15 MHz when the frequency of an input clock is 125 MHz. The designed frequency synthesizer using a multi-phase DLL-based phase selector has the area of 0.167 $mm^2$ and the peak-to-peak jitter performance of 2.88 ps when it consumes the power of 4.75 mW. The designed frequency synthesizer using a fractional-N PLL has the area of 0.662 $mm^2$ and the peak-to-peak jitter performance of 7.2 ps when it consumes the power of 1.16 mW.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.47 no.12
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• pp.75-82
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• 2010

This paper presents a wideband ${\Delta}{\Sigma}$ fractional-N frequency synthesizer for a multi-band single chip CMOS RFIC transceivers. A wideband VCO utilizes a 6-bit switched capacitor array bank for 2340~3940 MHz frequency range. VCO frequency calibration circuit is designed for optimal capacitor bank code selection before phase locking process. It finishes the calibration process in $2{\mu}s$ over the whole frequency band. The LO generation block has selectable multiple division ratios of ${\div}2$, ${\div}16$, and ${\div}32$ to generate LO I/Q signals for T-DMB/DAB/FM Radio systems in L-Band (1173~1973 MHz), VHF-III (147~246 MHz), VFH-II (74~123 MHz), respectively. The measured integrated phase noise is quite low as it is lower than 0.8 degree RMS over the whole frequency band. Total locking time of the ${\Delta}{\Sigma}$ frequency synthesizer including VCO frequency calibration time is less than $50{\mu}s$. The wideband ${\Delta}{\Sigma}$ fractional-N frequency synthesizer is fabricated in $0.13{\mu}m$ CMOS technology, and it consumes 15.8 mA from 1.2 V DC supply.

• Proceedings of the Korean Society of Precision Engineering Conference
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• 2012.05a
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• pp.299-300
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• 2012