• Title/Summary/Keyword: 분석 칩

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Analysis of Chip Performance by Core and I/O SSN Noise on DLL Board (DLL 보드 상에 코어 및 I/O 잡음에 의한 칩의 성능 분석)

  • Cho, Sung-Gon;Ha, Jong-Chan;Wee, Jae-Kyung
    • Journal of the Microelectronics and Packaging Society
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    • v.13 no.4
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    • pp.9-15
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    • 2006
  • This paper shows the impedance profile of PEEC(Partial Equivalent Electrical Circuit) PDN(Power Distribution Networks) including core and I/O circuit. Through the simulated results, we find that the core power noise having connection with I/O power is affected by I/O switching. Also, using designed $74{\times}5inch$ DLL(Delay Locked Loop) test board, we analyzed the effect of power noise on operation region of chip. Jitter of a DLL measure for frequency of $50{\sim}400MHz$ and compared with impedance obtained result of simulation. Jitter of a DLL are increased near about frequency of 100MHz. It is reason that the resonant peak of PDNs has an impedance of more the 1ohm on 100MHz. we present the impedance profile of a chip and board for the decoupling capacitor reduced the target impedance. Therefore, power supply network design should be considered not only decoupling capacitors but also core switching current and I/O switching current.

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Thermal Cycling and High Temperature Storage Reliabilities of the Flip Chip Joints Processed Using Cu Pillar Bumps (Cu Pillar 플립칩 접속부의 열 싸이클링 및 고온유지 신뢰성)

  • Kim, M.Y.;Lim, S.K.;Oh, T.S.
    • Journal of the Microelectronics and Packaging Society
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    • v.17 no.3
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    • pp.27-32
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    • 2010
  • For the flip chip joints processed using Cu pillar bumps and Sn pads, thermal cycling and high temperature storage reliabilities were examined as a function of the Sn pad height. With increasing the height of the Sn pad, which composed of the flip chip joint, from 5 ${\mu}m$ to 30 ${\mu}m$, the contact resistance of the flip chip joint decreased from 31.7 $m{\Omega}$ to 13.8 $m{\Omega}$. Even after thermal cycles of 1000 times ranging from $-45^{\circ}C$ to $125^{\circ}C$, the Cu pillar flip chip joints exhibited the contact resistance increment below 12% and the shear failure forces similar to those before the thermal cycling test. The contact resistance increment of the Cu pillar flip chip joints was maintained below 20% after 1000 hours storage at $125^{\circ}C$.

A Study on the Practical Application of Image Control Point Using Stereo Image Chip (입체 영상칩을 이용한 영상기준점 활용방안에 관한 연구)

  • Kim, Hoon-Jung;Kim, Kam-Lae;Cheong, Hae-Jin;Cho, Won-Woo
    • Journal of the Korean Society of Surveying, Geodesy, Photogrammetry and Cartography
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    • v.26 no.4
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    • pp.423-431
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    • 2008
  • The control surveying which aims at identifying the coordinate system of satellite images with that of ground is a repeatedly performed essential process to produce digital ortho - photos and it acts as the main factor to increase the production cost of the photos by duplicated budgets and redundant works when executing the projects for acquiring basic geographical information from high density satellite images. During the experimentation, an application system was established for producing a stereo image chip by the analysis of DPPDB file structure, the stereo image chip was produced with SPOT and IKONOS images, the analysis of 3D modeling accuracy was performed to secure the required accuracy and to present the optimal number and deployment of the control points, and a 3D modeling was performed for new SPOT images and lastly, 3D ground coordinates were extracted by the observation of the same points through the overlapping with the new images. As the results of the research, it is proved that the stereo image chip can be used as the ground controls through the accuracy analysis between the coordinates of the images and the ground, close results were obtained between the coordinates by the ground survey and those by the 3D modeling using new images and the observation of the same points, positional changes were not found during observing the same points, and the research presented the methodology for improving the process of the control survey by showing the availability of the image controls on the stereo image chip instead of the ground controls.

The Scattering Beam Measurement of the RBC and the Fabrication of the Micro Cell Biochip (적혈구의 산란빔 측정과 마이크로 세포 분석 바이오칩 제작)

  • Byun, In Soo;Kwon, Ki Jin;Lee, Joon Ha
    • Progress in Medical Physics
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    • v.25 no.2
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    • pp.116-121
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    • 2014
  • Next future, The bio technology will be a rapidly developing. This paper is the scattering beam measurement of the red blood cell (RBC) and the fabrication of the micro cell biochip using the bio micro electro mechanical system (Bio-MEMS) process technology. The Major process method of Bio-MEMS technology was used the buffered oxide etchant (BOE), electro chemical discharge (ECD) and ultraviolet sensitive adhesives (UVSA). All experiments were the 10 times according to the process conditions. The experiment and research are required the ultraviolet expose, the micro fluid current, the cell control and the measurement of the output voltage Vpp (peak to peak) waveform by scattering angles. The transmitting and receiving of the laser beam was used the single mode optical fiber. The principles of the optical properties are as follows. The red blood cells were injected into the micro channel. The single mode optical fiber was inserting in the guide channel. The He-Ne laser beam was focusing in the single mode optical fiber. The transmission He-Ne laser beam is irradiating to the red blood cells. The manufactured guide channel consists of the four inputs and the four outputs. The red blood cell was allowed with the cylinder pump. The output voltage Vpp waveform of the scattering beam was measured with a photo detector. The receiving angle of the output optical fiber is $0^{\circ}$, $5^{\circ}$, $10^{\circ}$, $15^{\circ}$. The magnitude of the output voltage Vpp waveform was measured in the decrease according to increase of the reception angles. The difference of the output voltage Vpp waveform is due differences of the light transmittance of the red blood cells.

Change in Flavor Components of Black-fermented Garlic Wine according to the Type of Chips during the Manufacturing Process (흑마늘와인 제조과정 중 숙성칩의 종류에 따른 향기성분 변화)

  • Kim, Gyeong-Hwan;Kim, Jin-Hee;Yang, Ji-Young
    • Journal of Food Hygiene and Safety
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    • v.29 no.1
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    • pp.73-77
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    • 2014
  • Black fermented garlic includes many pharmacological components. Therefore, in this study, black fermented garlic wine was manufactured and its flavor compounds were investigated difference of aging chips from America and France. The fermented wine was stored at $10^{\circ}C$ for 6 months. GC/MS was used for the flavor components analysis. Wine using American chip contained 2-methyl-1-propanol, 3-methyl-1-butanol, 2-methyl-1-butanol, acetaldehyde, butanoic acid, octanoic acid, 1,1-diethoxyethane, and allyl methyl sulfide. 1-Propanol, 2-methyl-1-propanol, 3-methyl-1-butanol, acetaldehyde, acetic acid, propanoic acid, butanoic acid, octanoic acid, 2-heptanone, 1,1-diethoxyethane, N-amino32-hydroxypropanamidate, n-butylamine, and chloroacetonitrile were detected as major flavor compounds using France chips. Especially, the wine contained allyl methyl sulfide that was resulted from black fermented garlic. There were more compounds that smell like fruit in the wine using American chips relatively. And allyl methyl sulfide was detected only in the wine using America chips. Whereas acetic acid was detected only in the wine using France chips.

A study on the synchronization parameter to design ADSL chip in DMT systems (DMT시스템에서 ADSL 칩 설계를 위한 동기화 파라미터에 관한 연구)

  • Cho, Byung-Lok;Park, Sol;Kim, Young-Min
    • Journal of the Korea Institute of Information and Communication Engineering
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    • v.3 no.3
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    • pp.687-694
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    • 1999
  • In this paper, to draw out the parameter of synchronization for ADSL(Asymmetric Digital Subscriber Line) chip design, we analyze the performance of STR(Symbol Timing Recovery) and frame synchronization with computer simulation. We analyze and design PLL(Phase Lock Loop) loop for ADSL. As a result, we obtained the optimum parameter of STR to design ADSL chip. Also, when performed frame synchronization with several algorithm, we analyzed the performance of FER(Frame Error Rate) and the effect of frame offset with computer simulation.

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Analysis of Optimal Resolution and Number of GCP Chips for Precision Sensor Modeling Efficiency in Satellite Images (농림위성영상 정밀센서모델링 효율성 재고를 위한 최적의 해상도 및 지상기준점 칩 개수 분석)

  • Choi, Hyeon-Gyeong;Kim, Taejung
    • Korean Journal of Remote Sensing
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    • v.38 no.6_1
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    • pp.1445-1462
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    • 2022
  • Compact Advanced Satellite 500-4 (CAS500-4), which is scheduled to be launched in 2025, is a mid-resolution satellite with a 5 m resolution developed for wide-area agriculture and forest observation. To utilize satellite images, it is important to establish a precision sensor model and establish accurate geometric information. Previous research reported that a precision sensor model could be automatically established through the process of matching ground control point (GCP) chips and satellite images. Therefore, to improve the geometric accuracy of satellite images, it is necessary to improve the GCP chip matching performance. This paper proposes an improved GCP chip matching scheme for improved precision sensor modeling of mid-resolution satellite images. When using high-resolution GCP chips for matching against mid-resolution satellite images, there are two major issues: handling the resolution difference between GCP chips and satellite images and finding the optimal quantity of GCP chips. To solve these issues, this study compared and analyzed chip matching performances according to various satellite image upsampling factors and various number of chips. RapidEye images with a resolution of 5m were used as mid-resolution satellite images. GCP chips were prepared from aerial orthographic images with a resolution of 0.25 m and satellite orthogonal images with a resolution of 0.5 m. Accuracy analysis was performed using manually extracted reference points. Experiment results show that upsampling factor of two and three significantly improved sensor model accuracy. They also show that the accuracy was maintained with reduced number of GCP chips of around 100. The results of the study confirmed the possibility of applying high-resolution GCP chips for automated precision sensor modeling of mid-resolution satellite images with improved accuracy. It is expected that the results of this study can be used to establish a precise sensor model for CAS500-4.

Chip Breaking Prediction Using AE Signal (AE신호에 의한 칩 절단성 예측)

  • 최원식
    • Journal of the Korean Society of Manufacturing Technology Engineers
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    • v.8 no.4
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    • pp.61-67
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    • 1999
  • In turning the chip may be produced in the form of continuous chip or discontinuous one. Continuous chips produced at high speed machining may hit the newly cut workpiece surface and adversely affect the appearance of the surface finish and may interfere with tool and sometimes induce tool fracture. In this study relationship between AE signal and chip form was experimentally investigated, The experimental results show that types of chip form are possible to be classified from the AE signal using fuzzy logic.

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The Issues and the Technology Trends of LED (LED의 이슈 및 기술 동향)

  • Kim, J.
    • Electronics and Telecommunications Trends
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    • v.24 no.6
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    • pp.61-76
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    • 2009
  • LED는 2000년대에 들어서면서 생활 전반에 사용되기 시작하여 최근에는 자동차용 부품과 TV의 back light unit에 이르기까지 모든 분야에서 다양한 용도로 사용되고 있다. 본 기고에서는 이러한 LED의 기판을 포함한 에피, 칩, 그리고 패키지 기술의 중요한 이슈와 기술의 동향에 대하여 간략히 정리하였다. 상용화되어 사용되는 사파이어나 SiC 기판 이외에 연구개발이 진행중인 GaN 기판 기술 등을 소개하고, 에피 기술에서는 활성층과 클래딩층 성장 기술의 이슈들을 제시하며, 칩의 종류와 특성을 중심으로 droop 현상과 광추출 기술 등을 살펴보고, 다양한 패키지의 종류 및 특징 등을 포함하는 LED 분야의 기술 동향에 대하여 설명한다.

Silicon Photonics Technology-The optical I/O platform for future computing and data communication (실리콘 포토닉스 테크놀로지-미래컴퓨팅, 데이터 통신을 위한 광I/O 플랫폼)

  • Kim, G.
    • Electronics and Telecommunications Trends
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    • v.31 no.6
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    • pp.13-20
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    • 2016
  • 실리콘 포토닉스 기술은 컴퓨터를 비롯한 여러 전자, 통신 기기들이 광 정보를 송수신하는 데 표준 실리콘을 이용하는 기술로, 기존 실리콘 반도체 기술과 호환될 수 있는 기술이다. 전자와 광의 융합기술로 실리콘 칩 사이, 또는 칩 내에서 빛으로 데이터를 주고받아, 데이터 전송속도를 획기적으로 올리면서도 전력 소모량을 크게 줄일 수 있는 것이 가능하다. 고성능, 저 생산비용과 낮은 소비전력 등의 장점 때문에, 전 세계적으로 실리콘 포토닉스 핵심기술/실용적 플랫폼 연구개발 및 상용화 경쟁이 이루어지고 있다. 본지에서는 실리콘 포토닉스 기술의 간략한 개요, 현재 동향 및 기술 이슈, 그리고 ETRI에서 연구개발된 실리콘 포토닉스 기술과 더불어 그 발전 전망에 대해 기술한다.

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