• The KIPS Transactions:PartA
• /
• v.16A no.5
• /
• pp.347-356
• /
• 2009

Precise branch prediction is a critical factor in the IPC Improvement of modern microprocessor architectures. In addition to the branch prediction accuracy, branch prediction delay have a profound impact on overall system performance as well. However, it tends to be overlooked when the architects design the branch predictor. To tolerate branch prediction delay, this paper proposes Early Start Prediction (ESP) technique. The proposed solution dynamically identifies the start instruction of basic block, called as Basic Block Start Address (BB_SA), and the solution uses BB_SA when predicting the branch direction, instead of branch instruction address itself. The performance of the proposed scheme can be further improved by combining short interval hiding technique between BB_SA and branch instruction. The simulation result shows that the proposed solution hides prediction latency, with providing same level of prediction accuracy compared to the conventional predictors. Furthermore, the combination with short interval hiding technique provides a substantial IPC improvement of up to 10.1%, and the IPC is actually same with ideal branch predictor, regardless of branch predictor configurations, such as clock frequency, delay model, and PHT size.

• Journal of the Institute of Electronics Engineers of Korea CI
• /
• v.44 no.1
• /
• pp.33-40
• /
• 2007

Processor pipelines have been growing deeper and issue widths wider over the years. If this trend continues, the branch misprediction penalty will become very high. Branch misprediction is the single most significant performance limiter for improving processor performance using deeper pipelining. Therefore, more accurate branch predictor becomes an essential part of modern processors. Several branch predictors combine a part of the branch address with a fixed amount of global branch history to make a prediction. These predictors cannot perform uniformly well across all programs because the best amount of branch history to be used depends on the program and branches in the program. Therefore, predictors that use a fixed history length are unable to perform up to their potential performance. In this paper, we propose a branch prediction mechanism, using variable length history, which predicts using a bank having higher prediction accuracy among predictions from five banks. Bank 0 is a bimodal predictor which is indexed with the 12 least significant bits of the branch address. Banks 1, 2, 3 and 4 are predictors which are indexed with different global history bits and the branch PC. In simulation results, the proposed mechanism outperforms gshare predictors using fixed history length of 12 and 13 , up to 6.34% in prediction accuracy. Furthermore, the proposed mechanism outperforms gshare predictors using best history lengths for benchmarks, up to 2.3% in prediction accuracy.

• Journal of the Institute of Electronics Engineers of Korea CI
• /
• v.42 no.1
• /
• pp.9-26
• /
• 2005

In the pursuit of ever higher levels of performance, recent computer systems have made use of deep pipeline, dynamic scheduling and multi-issue superscalar processor technologies. In this situations, branch prediction schemes are an essential part of modem microarchitectures because the penalty for a branch misprediction increases as pipelines deepen and the number of instructions issued per cycle increases. In this paper, we propose a novel branch prediction scheme, direction-gshare(d-gshare), to improve the prediction accuracy. At first, we model a neural network with the components that possibly affect the branch prediction accuracy, and analyze the variation of their weights based on the neural network information. Then, we newly add the component that has a high weight value to an original gshare scheme. We simulate our branch prediction scheme using Simple Scalar, a powerful event-driven simulator, and analyze the simulation results. Our results show that, compared to bimodal, two-level adaptive and gshare predictor, direction-gshare predictor(d-gshare. 3) outperforms, without additional hardware costs, by up to 4.1% and 1.5% in average for the default mont of embedded direction, and 11.8% in maximum and 3.7% in average for the optimal one.

• Journal of the Korea Society of Computer and Information
• /
• v.13 no.4
• /
• pp.19-30
• /
• 2008

Branch history is one of major input vectors in branch prediction. Therefore, the Proper use of branch history plays a critical role of improving branch prediction accuracy. To improve branch prediction accuracy, this paper proposes a new branch history management policy, based on interrelationship analysis of instructions. First of all, we propose three different algorithms to analyze the relationship: register-writhing method, branch-reading method, and merged method. Then we additionally propose variable input gshare predictor as an implementation of these algorithms. In simulation part, we provide performance differences among the algorithms and analyze their characteristics. In addition, we compare branch prediction accuracy between our proposals and conventional fixed input predictors. The performance comparison for optimal input branch predictor is also provided.

• Journal of the Institute of Electronics Engineers of Korea CI
• /
• v.44 no.2 s.314
• /
• pp.1-10
• /
• 2007

Branch prediction accuracy is critical for the overall system performance. Branch miss-prediction penalty is the one of the significant performance limiters for improving processor performance, as the pipeline deepens and the instruction issued per cycle increases. In this paper, we propose "Dynamic Per-Branch History Length Fitting Method" by tracking the data dependencies among the register writing instructions. The proposed solution first identifies the key branches, and then it selectively uses the histories of the key branches. To support this mechanism, we provide a history length adjustment algorithm and a required hardware module. As the result of simulation, the proposed mechanism outperforms the previous fixed static method, up to 5.96% in prediction accuracy. Furthermore, our method introduces the performance improvement, compared to the profiled results which are generally considered as the optimal ones.

• Proceedings of the Korean Information Science Society Conference
• /
• 2001.10c
• /
• pp.25-27
• /
• 2001

본 논문에서는 AE32000 프로세서에 적응 가능한 효율적인 분기 예측 기법에 관하여 연구하였다. 실험결과, 내장형 응용분야에서의 비용 효율성이란 측면에, AE32000 프로세서에서는 1비트의 분기 예측기와 한 개의 엔트리를 갖는 BTB(Branch Target Buffer)를 사용하는 것이 가장 적합함을 관찰하였다. 또한, 분기 목적 주소에서 나타나는 LERI 명령을 폴딩하여 분기 손실을 줄이는 방안은, BTB와 LERI 폴딩 유닛을 사용하는 설계에서, 가져오는 성능 향상이 미미함을 확인하였다.

• The Journal of Korean Institute of Communications and Information Sciences
• /
• v.38A no.12
• /
• pp.1094-1101
• /
• 2013

This paper proposes an improved branch predictor that reduces the number execution cycles of applications by selectively accessing a specific element in 4-way associative cache. When a branch instruction is fetched, the proposed branch predictor acquires a branch target address from the selected element in the cache by referring to MRU buffer. Branch prediction rate and application execution speed are considerably improved by increasing the number of BTAC entries in restricted power condition, when compared with that of previous branch predictor which accesses all elements. The effectiveness of the proposed dynamic branch predictor is verified by executing benchmark applications on the core simulator. Experimental results show that number of execution cycles decreases by an average of 10.1%, while power consumption increases an average of 7.4%, when compared to that of a core without a dynamic branch predictor. Execution cycles are reduced by 4.1% in comparison with a core which employs previous dynamic branch predictor.

• Journal of KIISE:Computer Systems and Theory
• /
• v.26 no.9
• /
• pp.1158-1165
• /
• 1999

조건부 분기 명령어(conditional branch instruction)의 잘못된 분기 예측(branch misprediction)은 프로세서의 성능 향상에 심각한 장애 요인이 되고 있다. 특히 시분할(time-sharing) 시스템과 같이 문맥 교환(context switch)이 발생하는 멀티프로그래밍 환경(multiprogramming environment)에서는 더욱 낮은 분기 예측 정확성(branch prediction accuracy)을 보인다. 본 논문에서는 문맥 교환이 발생하는 멀티프로그래밍 환경에서 높은 분기 예측 정확성을 보이는 중첩 분기 예측표 교환(Overlapped Predictor Table Switch, OPTS) 기법을 소개한다. 분기 예측표(predictor table)를 분할하여 각각의 프로세스(process)에 할당하는 OPTS 기법은 문맥 교환의 영향을 최소화함으로써 높은 분기 예측 정확성을 유지하는 분기 예측 방법이다.Abstract There is wide agreement that one of the most important impediments to the performance of current and future pipelined superscalar processors is the presence of conditional branches in the instruction stream. Accurate branch prediction is required to overcome this performance limitation. Many branch predictors have been proposed to help to alleviate this problem, including the two-level adaptive branch predictor, and more recently, hybrid branch predictor. In a less idealized environment, such as a time-sharing system, code of interest involves context switches. Context switches, even at fairly large intervals, can seriously degrade the performance of many of the most accurate branch prediction schemes. In this study, we measure the effect of context switch on the branch prediction accuracy in various situation and show the feasibility of our new mechanism, OPTS(Overlapped Predictor Table Switch), which save and restore branch history table at every context switch.

• Journal of Korean Society of Forest Science
• /
• v.84 no.2
• /
• pp.121-130
• /
• 1995

Forecasting accuracy is examined in the context of Michigan travel demand. Eight different annual models are used to forecast up to two years ahead, and nine different quarterly models up to four quarters. In the evaluation of annual models' performance, multiple regression performed better than the other methods in both the one year and two year forecasts. For quarterly models, Winters exponential smoothing and the Box-Jenkins method performed better than naive 1 s in the first quarter ahead, but these methods in the second, third, and fourth quarters ahead performed worse than naive 1 s. The sophisticated models did not outperform simpler models in producing quarterly forecasts. The best model, multiple regression, performed slightly better when fitted to quarterly rather than annual data: however, it is not possible to strongly recommend quarterly over annual models since the improvement in performance was slight in the case of multiple regression and inconsistent across the other models. As one would expect, accuracy declines as the forecasting time horizon is lengthened in the case of annual models, but the accuracy of quarterly models did not confirm this result.

• Proceedings of the Korean Information Science Society Conference
• /
• 2005.11a
• /
• pp.766-768
• /
• 2005

분기 영령어의 예측 정확도는 시스템 전체 성능에 중대한 영향을 미친다. 여러 분기 예측 방식 가운데 하나인 "분기 정보의 투기적 사용" 은 분기 명령어의 가장 최근 기록을 일관되게 사용할 수 있도록 도와줌으로 해서 분기 예측의 정확도 향상에 크게 기여한다. 하지만 이와 같은 기법은 미완료 분기에 대한 히스토리를 투기적으로 사용하는 방식이다. 따라서 사용되는 정보가 올바르지 못할 수 있으며, 이런 경우 적절한 복구 기법을 필요로 한다. 본 논문에서는 분기 정보의 투기적 사용에 대한 필요성과 효율적인 복구 기법을 제안한다. 제안된 기법은 이전 연구와 비교하여 상당한 하드웨어 요구량의 감소를 가져왔으며, 또한 프로그램 수행의 정확성을 해치지 않으면서 최대 $3.3\%$의 성능향상을 보였다.