• Title/Summary/Keyword: 부저항소자

Search Result 4, Processing Time 0.018 seconds

A Gain Enhancing Scheme for Op-Amp in High Performance AIPS Using Negative Resistance Element (고성능 AIPS 내의 연산증폭기에 대하여 부저항소자를 사용한 이득개선방법)

  • Chung Kang-Min;Kim Sung-Mook
    • The KIPS Transactions:PartA
    • /
    • v.12A no.6 s.96
    • /
    • pp.531-538
    • /
    • 2005
  • In the high performance Analog Information Processing Systems(AIPS), gain boosting or additional gain stage is required when the gain is not sufficient with one stage amplification. This work shows that high gain is neatly obtained by enhancing the gain using the negative resistance element. Compared to the conventional techniques, the proposed scheme enjoys full output swing, small circuit area and power consumption, and the applications to various configurations of amplifiers. The negative resistance element is placed between the differential output nodes when used in the Op-Amp. The HSPICE simulation indicates that enhancement of more than 40 dB is readily obtained in this simple configuration when the negative resistance element is implemented in the form of cross-coupled CMOS inverters.

Analysis of a Tunnel-Diode Oscillator Circuit by Predictor-Corrector Method (프레딕터.코렉터방법에 의한 터널다이오드 발진회로의 해석)

  • 이정한;차균현
    • Journal of the Korean Institute of Telematics and Electronics
    • /
    • v.10 no.6
    • /
    • pp.45-55
    • /
    • 1973
  • This paper discusses the nonlinear time-invarient circuit composed of a tunnel diode. Prior to determine the solution of the nonlinear network which has negative resistance elements, the static characteristics of the nonlinear resistance elements need to be represented by function. Polynomial curve fitting is discussed to represent the static characteristies by least squares approximation. In order to solve the nonlinear network, the state equations for the networks are set up and solved by prediction corrector method. Finally, the limit cycle is plotted to discuss the stability of the nonlinear network and the oscillation condition.

  • PDF

A Study on the MOCVD Growth and Characterization of Resonant Tunneling Structures (공명 투과 구조의 MOCVD 성장 및 특성에 관한 연구)

  • 류정호;서광석
    • The Journal of Korean Institute of Communications and Information Sciences
    • /
    • v.18 no.7
    • /
    • pp.1036-1043
    • /
    • 1993
  • GaAs/AIGaAs resonant tunneling structures have been grown by atmospheric pressure MOCVD. Resonant tunneling diodes fabricated with the structure grown at 650t showed a high peak-to-valley (P/V) current ratio of 2.35 at room temperature. P/V current ratio increased to 15.3 at 77K. Numerically calculated peak current agrees well with the experimental result. Resonant tunneling diodes with AIGaAs as a barrier and InGaAs as a quantum well and a spacer layer yielded a high P/V current ratio of 4.0 and a peak current density of 8.6KA/c# at room temperature because of increased carrier supply.

  • PDF

The Design of 10-bit 200MS/s CMOS Parallel Pipeline A/D Converter (10-비트 200MS/s CMOS 병렬 파이프라인 아날로그/디지털 변환기의 설계)

  • Chung, Kang-Min
    • The KIPS Transactions:PartA
    • /
    • v.11A no.2
    • /
    • pp.195-202
    • /
    • 2004
  • This paper introduces the design or parallel Pipeline high-speed analog-to-digital converter(ADC) for the high-resolution video applications which require very precise sampling. The overall architecture of the ADC consists of 4-channel parallel time-interleaved 10-bit pipeline ADC structure a]lowing 200MSample/s sampling speed which corresponds to 4-times improvement in sampling speed per channel. Key building blocks are composed of the front-end sample-and-hold amplifier(SHA), the dynamic comparator and the 2-stage full differential operational amplifier. The 1-bit DAC, comparator and gain-2 amplifier are used internally in each stage and they were integrated into single switched capacitor architecture allowing high speed operation as well as low power consumption. In this work, the gain of operational amplifier was enhanced significantly using negative resistance element. In the ADC, a delay line Is designed for each stage using D-flip flops to align the bit signals and minimize the timing error in the conversion. The converter has the power dissipation of 280㎽ at 3.3V power supply. Measured performance includes DNL and INL of +0.7/-0.6LSB, +0.9/-0.3LSB.