• The Transactions of the Korea Information Processing Society
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• v.3 no.2
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• pp.242-250
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• 1996

Communications on hypercube nodes are done by explicit message routing. So efficient message routing is very important for the performance of hypercube multicomputers. However, hypercube nodes can be faulty due to hardware and/o r software problems, which is called an injured hypercube. A reliable hypercube system should tolerate the problems. One of the methods to enhance reliability on injured hypercube is to use fault-tolerant message routing algorithms. In this paper, we propose a message routing algorithm with possible shortest distance using disjoint paths. To analyze the performance, the algorithm is simulated and evaluated.

• Journal of the Institute of Electronics Engineers of Korea SC
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• v.43 no.5 s.311
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• pp.44-59
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• 2006

This paper describes the efficient implementation of DNA sequence generate system with genetic algorithm for reducing computation time of NACST. The proposed processor is based on genetic algerian with fitness functions which would suit the point of reference for generated sequences. In order to implement efficient hardware structure, we used the pipelined structure. In addition our design was applied the parallelism to achieve even better simulation time than the sequence generator system which is designed on software. In this paper, our hardware is implemented on the FPGA board with xc2v6000 devices. Through experiment, the proposed hardware achieves 467 times speed-up over software on a PC and sequence generate performance of hardware is same with software.

• Journal of KIISE:Databases
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• v.28 no.4
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• pp.665-676
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• 2001

The most expensive spatial operation in patial database in a spatial join which computes a combined table of which tuple consists of two tuples of the two tables satisgying a spatial predicate. Although the execution time of sequential processing of a spatial join has been so far considerably improved the response time is not tolerable because of not meeting the requiremetns of interactive users. It is usually appropriate to use parallel processing to improve the performance of spatial join processing. in spatial database the fixed grids which consist of the regularly partitioned cells can be employed the previous works on the spatial joins have not studied the parallel processing of spatial joins using fixed grids. This paper has presented an analytical cost model that estimates the comparative performance of a parallel spatial join algorithm based on the fixed grids in terms of the number of MBR comparisons. disk accesses, and message passing, Several experiments on the synthetic and real datasets show that the proposed analytical model is very accurate. This most model is also expected to used for implementing a very important DBMS component, Called the query processing optimizer.

• Proceedings of the Korea Information Processing Society Conference
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• 2014.04a
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• pp.33-36
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• 2014

최근 스마트폰이나 태블릿 PC 등의 모바일 디바이스가 상용화 되어감에 따라 그 안에서 핵심적인 처리기능을 담당하는 프로세서의 코어 수가 점차적으로 늘어나고 있다. 많은 수의 코어를 효율적으로 사용하기 위해 여러 가지 메커니즘이 구현되어 있으나, 단일 프로세스를 순차적으로 실행하는 경우 여전히 성능에서의 한계가 존재한다. 병렬화 되어 있지 않은 프로세스의 경우, Amdahl's Law[1]에 따르면 순차적으로 실행을 할 수 밖에 없는 부분이 존재하고, 이 부분은 하나의 코어에서만 실행되기 때문에 많은 연산 자원들이 낭비되는 현상이 발생한다. 본 논문은 다중 코어 환경에서 이러한 잉여자원을 효과적으로 사용하기 위해 Back-end Fusion 이라는 구조를 제안하여 프로세서의 성능 향상을 위한 연구를 진행하였다. Back-end Fusion 이란, 연산 처리를 담당하는 back-end 부분(execution unit, writeback 단계 등)을 필요에 따라 코어 간에 동적으로 재구성하여 성능을 향상시키는 메커니즘이다. 이 재구성된 프로세서의 back-end 를 효율적으로 사용하기 위해, 종속성과 로드 밸런스 등을 고려한 인스트럭션 분배 알고리즘을 함께 제안한다. Intel 사의 x86 Instruction Set Architecture(ISA)를 기반으로 한 시뮬레이터를 이용하여 Back-end Fusion 프로세서의 성능을 측정 해 본 결과 기존의 단일 코어 프로세서에 비해 평균 32.2%의 성능 향상을 확인할 수 있었다.

• Journal of KIISE:Computer Systems and Theory
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• v.37 no.2
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• pp.66-75
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• 2010

This paper proposes an efficient method for design and implementation of the artificial intelligence (AI) of 'omok' game on the GPU. The proposed AI is designed on a cooperative structure using min-max game tree and genetic algorithm. Since the evaluation function needs intensive computation but is independently performed on a lot of candidates in the solution space, it is computed on the GPU in a massive parallel way. The implementation on NVIDIA CUDA and the experimental results show that it outperforms significantly over the CPU, in which parallel game tree and genetic algorithm on the GPU runs more than 400 times and 300 times faster than on the CPU. In the proposed cooperative AI, selective search using genetic algorithm is performed subsequently after the full search using game tree to search the solution space more efficiently as well as to avoid the thread overflow. Experimental results show that the proposed algorithm enhances the AI significantly and makes it run within the time limit given by the game's rule.

• Proceedings of the Korean Society of Broadcast Engineers Conference
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• 2009.11a
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• pp.173-176
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• 2009

본 논문에서는 영상 정보와 오디오 정보 분석을 이용하여 TV 골프 방송 프로그램에서 중요 이벤트 구간을 검출하고 요약 하는 알고리즘을 제안한다. 제안하는 알고리즘에서는 입력되는 TV 골프 동영상을 영상 신호와 오디오 신호로 분리한 후에, 연속적인 오디오 스트림을 내용 기반의 오디오 구간으로 분류한 뒤 오디오 이벤트 구간을 검출하고, 이와 병렬적으로 영상정보에서 선수들의 플레이 장면을 검출한다. 플레이 장면 검출에 있어서는 방송 환경이나 날씨 등의 변화하는 다양한 조건에 대해 플레이 장면에 대한 오프라인 모델과 함께 경기 내에서 발생한 온라인 모델에 대한 학습을 혼합 적용함으로써 검출 성능을 높였다. 오디오 신호로부터 관중들의 박수소리와 스윙 사운드를 통해 검출된 오디오 이벤트와 플레이 장면은 이벤트 장면 검출 및 요약본 생성을 위해 사용된다. 제안된 알고리즘은 멀티 모달 정보를 이용하여 이벤트 구간 검출을 수행함으로써 중요 이벤트 구간 검출의 정확도를 높일 수 있었고, 검출된 이벤트 구간에 대한 요약본 생성을 통해 골프 경기를 시청하는 사용자가 원하는 부분을 빠르게 브라우징하여 시청하는 것이 가능하여 높은 사용자 만족도를 얻을 수 있었다.

• The Transactions of the Korea Information Processing Society
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• v.4 no.3
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• pp.871-879
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• 1997

The comversion of printed maps into computerixed data bases is an enormous rask. Thus the autmaotion of the conversion process is essential. Efficient computer representation of printed maps and line drawings depends on codes assigened to chracaters, symbools, and vestor representation of the graphics. In many cases, maps ard constructed in a number of layers, where each layer is printed in a distinct color, and it represents a subste of the map infromation. In order to properly repressnet road information from color map images, an automatic road extraction algorithm is proposed. Road image is separated from graghics by color segmentation, and then restored by the proposed concurrent conditional dilation operation. The internal and external noise of the road image is eliminated by opening and closing operation. By thining and vectorizing line segments, the desited road information is extracted.

• Journal of Advanced Navigation Technology
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• v.24 no.4
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• pp.291-298
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• 2020

This study proposed a model that can track MPP faster than the existing MPPT algorithm using the particle swarm optimization algorithm (PSO). The proposed model highly sets the acceleration constants of gbest and pbest in the PSO algorithm to quickly track the MPP point and eliminates the power instability problem. In addition, this algorithm was re-executed by detecting the change in power of the solar panel according to the rapid change in solar radiation. As a result of the experiment, MPP time was 0.03 seconds and power was 131.65 for 691.5 W/m2, and MPP was tracked at higher power and speed than the existing P&O and INC algorithms. The proposed model can be applied when a change in the amount of power is detected by partial shading in a Photovoltaic power plant with Photovoltaic connected in parallel. In order to improve the MPPT algorithm, this study needs a comparative study on optimization algorithms such as moth flame optimization (MFO) and whale optimization algorithm (WOA).

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.40 no.3
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• pp.33-42
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• 2003

This paper describes an efficient design of an asynchronous 16-bit divider using the NST (new Svoboda-Tung) algorithm. The divider is designed to reduce power consumption by using the asynchronous design scheme in which the division operation is performed only when it is requested. The divider consists of three blocks, i.e. pre-scale block, iteration step block, and on-the-fly converter block using asynchronous pipeline structure. The pre-scale block is designed using a new subtracter to have small area and high performance. The iteration step block consists of an asynchronous ring structure with 4 division steps for area reduction. In other to reduce hardware overhead, the part related to critical path is designed by a dual-rail circuit, and the other part is done by a single-rail circuit in the ring structure. The on-the-fly converter block is designed for high performance using the on-the-fly algorithm that enables parallel operation with iteration step block. The design results with 0.6${\mu}{\textrm}{m}$ CMOS process show that the divider consists of 12,956 transistors with 1,480 $\times$1,200${\mu}{\textrm}{m}$$^2$area and average-case delay is 41.7㎱.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.35 no.2C
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• pp.148-154
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• 2010

In this paper, we first review LDPC codes in general and a belief propagation algorithm that works in logarithm domain. LDPC codes, which is chosen 802.11n for wireless local access network(WLAN) standard are required a large number of computation due to large size of coded block and iteration. Therefore, we presented three kinds of low computational algorithm for LDPC codes. First, sequential decoding with partial group is proposed. It has same H/W complexity, and fewer number of iteration's are required at same performance in comparison with conventional decoder algorithm. Secondly, we have apply early stop algorithm. This method is reduced number of unnecessary iteration. Third, early detection method for reducing the computational complexity is proposed. Using a confidence criterion, some bit nodes and check node edges are detected early on during decoding. Through the simulation, we knew that the iteration number are reduced by half using subset algorithm and early stop algorithm is reduced more than one iteration and computational complexity of early detected method is about 30% offs in case of check node update, 94% offs in case of check node update compared to conventional scheme.