• Title/Summary/Keyword: 복소수 데이터

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Development of the EM Wave Absorber for ETC of ITS (ITS의 ETC용 전파흡수체 개발)

  • Song, Young-Man;Choi, Chang-Mook;Lee, Dae-Hee;Kim, Dong-Il
    • Journal of Navigation and Port Research
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    • v.31 no.8
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    • pp.671-674
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    • 2007
  • In this paper, the EM wave absorber was designed and fabricated for ETC system, because ETC system has some problems including signal error and system-to-system interference. We fabricated some samples in different composition ratio of MnZn-ferrite, Carbon and CPE, confirmed that optimum composition ratio of Mn2n-ferrite, Carbon, CPE was 40 : 15 : 45 wt%. Complex relative permittivity and complex relative permeability was calculated by the measured data. And absorption abilities were simulated according to different thickness of the EM wave absorbers using complex relative permittivity and permeability. The EM wave absorber was fabricated based on simulated data Simulated and measured values agree well. As a result, the developed EM wave absorber has a thickness of 3.38 mm and absorption ability over 20 dB at 5.8 GHz.

New Parallel MDC FFT Processor for Low Computation Complexity (연산복잡도 감소를 위한 새로운 8-병렬 MDC FFT 프로세서)

  • Kim, Moon Gi;Sunwoo, Myung Hoon
    • Journal of the Institute of Electronics and Information Engineers
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    • v.52 no.3
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    • pp.75-81
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    • 2015
  • This paper proposed the new eight-parallel MDC FFT processor using the eight-parallel MDC architecture and the efficient scheduling scheme. The proposed FFT processor supports the 256-point FFT based on the modified radix-$2^6$ FFT algorithm. The proposed scheduling scheme can reduce the number of complex multipliers from eight to six without increasing delay buffers and computation cycles. Moreover, the proposed FFT processor can be used in OFDM systems required high throughput and low hardware complexity. The proposed FFT processor has been designed and implemented with a 90nm CMOS technology. The experimental result shows that the area of the proposed FFT processor is $0.27mm^2$. Furthermore, the proposed eight-parallel MDC FFT processor can achieve the throughput rate up to 2.7 GSample/s at 388MHz.

Aberration Retrieval Algorithm of Optical Pickups Using the Extended Nijboer-Zernike Approach (확장된 네이보어-제르니케 방법에 의한 광픽업의 파면수차 복원 알고리즘)

  • Jun, Jae-Chul;Chung, Ki-Soo;Lee, Gun-Kee
    • Journal of the Institute of Convergence Signal Processing
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    • v.11 no.1
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    • pp.32-40
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    • 2010
  • In this work, the method of acquiring the pupil function of optical system is proposed. The wavefront aberration and the intensity distribution of pupil can be analysed with the pupil function. This system can be adopted to the manufacturing line of optical pickup directly and also has good performance to analysing various property of optical instrument. It is one kind of inverse problem to get pupil functions by 3D beam data. The extended Nijboer-Zernike(ENZ) approach recently proposed by Netherlands research group is adopted to accompany to solve these inverse problem. The ENZ approach is one of a aberration retrieval method for which numerous approaches are available. But this approach is new in the sense that it use the highly efficient representation of pupil functions by means of their Zernike coefficients. These coefficients are estimated by using matching procedure in the focal region the theoretical 3D intensity distribution and measured 3D intensity distribution. The algorithm that can be applied more general circumstance such as high-numerical aperture instrument is developed by modifying original ENZ approach. By these scheme, MS windows based GUI program is developed and the good performance is verified with generated 3D beam data.

High Speed 8-Parallel Fft/ifft Processor using Efficient Pipeline Architecture and Scheduling Scheme (효율적인 파이프라인 구조와 스케줄링 기법을 적용한 고속 8-병렬 FFT/IFFT 프로세서)

  • Kim, Eun-Ji;SunWoo, Myung-Hoon
    • The Journal of Korean Institute of Communications and Information Sciences
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    • v.36 no.3C
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    • pp.175-182
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    • 2011
  • This paper presents a novel eight-parallel 128/256-point mixed-radix multi-path delay commutator (MRMDC) FFT/IFFT processor for orthogonal frequency-division multiplexing (OFDM) systems. The proposed FFT architecture can provide a high throughput rate and low hardware complexity by using an eight-parallel data-path scheme, a modified mixed-radix multi-path delay commutator structure and an efficient scheduling scheme of complex multiplications. The efficient scheduling scheme can reduce the number of complex multipliers at the second stage from 88 to 40. The proposed FFT/IFFT processor has been designed and implemented with the 90nm CMOS technology. The proposed eight-parallel FFT/IFFT processor can provide a throughput rate of up to 27.5Gsample/s at 430MHz.

Pre-processing Scheme for Indoor Precision Tracking Based on Beacon (비콘 기반 실내 정밀 트래킹을 위한 전처리 기법)

  • Hwang, Yu Min;Jung, Jun Hee;Shim, Issac;Kim, Tae Woo;Kim, Jin Young
    • Journal of Satellite, Information and Communications
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    • v.11 no.4
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    • pp.58-62
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    • 2016
  • In this paper, we propose a pre-processing scheme for improving indoor positioning accuracy in impulsive noise channel environments. The impulsive noise can be generated by multi-path fading effects by complicated indoor structures or interference environments, which causes an increase in demodulation error probability. The proposed pre-processing scheme is performed before a triangulation method to calculate user's position, and providing reliable input data demodulated from a received signal to the triangulation method. Therefore, we studied and proposed an adaptive threshold function for mitigation of the impulsive noise based on wavelet denoising. Through results of computer simulations for the proposed scheme, we confirmed that Bit Error Rate and Signal-to-Noise Ratio performance is improved compared to conventional schemes.

VLSI Design of a 2048 Point FFT/IFFT by Sequential Data Processing for Digital Audio Broadcasting System (순차적 데이터 처리방식을 이용한 디지틀 오디오 방송용 2048 Point FFT/IFFT의 VLSI 설계)

  • Choe, Jun-Rim
    • Journal of the Institute of Electronics Engineers of Korea SD
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    • v.39 no.5
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    • pp.65-73
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    • 2002
  • In this paper, we propose and verify an implementation method for a single-chip 2048 complex point FFT/IFFT in terms of sequential data processing. For the sequential processing of 2048 complex data, buffers to store the input data are necessary. Therefore, DRAM-like pipelined commutator architecture is used as a buffer. The proposed structure brings about the 60% chip size reduction compared with conventional approach by using this design method. The 16-point FFT is a basic building block of the entire FFT chip, and the 2048-point FFT consists of the cascaded blocks with five stages of radix-4 and one stage of radix-2. Since each stage requires rounding of the resulting bits while maintaining the proper S/N ratio, the convergent block floating point (CBFP) algorithm is used for the effective internal bit rounding and their method contributed to a single chip design of digital audio broadcasting system.

A case study of ground subsidence analysis using the InSAR technique (InSAR 기술을 이용한 지반침하분석 사례연구)

  • Moon, Joon-Shik;Oh, Hyoung-seok
    • Journal of Korean Tunnelling and Underground Space Association
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    • v.24 no.2
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    • pp.171-182
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    • 2022
  • InSAR (Interferometry SAR) technique is a technique that uses complex data to obtain phase difference information from two or more SAR image data, and enables high-resolution image extraction, surface change detection, elevation measurement, and glacial change observation. In many countries, research on the InSAR technique is being conducted in various fields of study such as volcanic activity detection, glacier observation in Antarctica, and ground subsidence analysis. In this study, a case of large ground settlement due to groundwater level drawdown during tunnelling was introduced, and ground settlement analyses using InSAR technique and numerical analysis method were compared. The maximum settlement and influence radius estimated by the InSAR technique and numerical method were found to be quite similar, which confirms the reliability of the InSAR technique. Through this case study, it was found that the InSAR technique reliable to use for estimating ground settlement and can be used as a key technology to identify the long-term ground settlement history in the absence of measurement data.

Low-power FFT/IFFT Processor for Wireless LAN Modem (무선 랜 모뎀용 저전력 FFT/IFFT프로세서 설계)

  • Shin Kyung-Wook
    • The Journal of Korean Institute of Communications and Information Sciences
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    • v.29 no.11A
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    • pp.1263-1270
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    • 2004
  • A low-power 64-point FFT/IFFT processor core is designed, which is an essential block in OFDM-based wireless LAM modems. The radix-2/418 DIF (Decimation-ln-Frequency) FFT algorithm is implemented using R2SDF (Radix-2 Single-path Delay Feedback) structure. Some design techniques for low-power implementation are considered from algorithm level to circuit level. Based on the analysis on infernal data flow, some unnecessary switching activities have been eliminated to minimize power dissipation. In circuit level, constant multipliers and complex-number multiplier in data-path are designed using truncation structure to reduce gate counts and power dissipation. The 64-point FFT/IFFT core designed in Verilog-HDL has about 28,100 gates, and timing simulation results using gate-level netlist with extracted SDF data show that it can safely operate up to 50-MHz@2.5-V, resulting that a 64-point FFT/IFFT can be computed every 1.3-${\mu}\textrm{s}$. The functionality of the core was fully verified by FPGA implementation using various test vectors. The average SQNR of over 50-dB is achieved, and the average power consumption is about 69.3-mW with 50-MHz@2.5-V.

Network design for correction of deterioration due to hologram compression (홀로그램 압축으로 인한 열화 보정을 위한 네트워크 설계)

  • Song, Joon Boum;jang, Junhyuck;Hwang, Yunseok;Cho, Inje
    • Proceedings of the Korean Society of Broadcast Engineers Conference
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    • 2020.11a
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    • pp.377-379
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    • 2020
  • The hologram data is having a dependence on the pixel pitch of the SLM (spatial light modulator) and the wavelength of light, and the quality of the digital hologram is proportional to the unit pixel pitch and the total resolution. In addition, since each pixel has a complex value, the amount of data in the digital hologram also increases exponentially, and the size is bound to be very large. Therefore, in order to efficiently handle digital hologram files, it is essential to reduce the file size through a codec and store it. Recently, research on enhancing image quality damaged by the codec is actively underway. In this paper, the hologram image of JPEG Pleno, which is the standard hologram data, was used, and the image quality damage that occurs whenthe holographic image is encoded and decoded through the JPEG2000, AVC, and HEVC codec is enhanced with a deep learning network to find out whether the image quality can be improved. we also compare and quantitatively find out the degree of improvement in image quality.

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The Study on the Performance of DS/CDMA with a Suppressed Pilot Channel in Mobile Satellite Communication System (이동위성 통신 시스템에서 억압 파일롯트 채널을 이용한 DS / CDMA의 성능 분석)

  • Chung, Boo-Young;Choi, Bong-Keun;Kang, Young-Heung;Lee, Jin
    • The Journal of Korean Institute of Electromagnetic Engineering and Science
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    • v.8 no.2
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    • pp.151-160
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    • 1997
  • In this paper, we have carried out the DS/CDMA with a suppressed pilot channel, which is used in receiving coherently with Rake diversity and in synchronizing the chip timing, in the mobile satellite communication. Also, we have investigated the envelope variation of a shadowed Rician fading simulator, and analyzed the error performences of DS/CDMA in the mobile satellite communication. The results showed that the error performance in the Heavy shadowing environment might be degraded more than in the Rayleigh fading environment since the fading envelopes in the former environment are varied randomly compared with those in the latter environment. And the performence of DS/CDMA system could be improved about 10 dB compared with that of narrowband QPSK system. In conclusion, DS/CDMA with a suppressed pilot channel had the best performance in the case of the suppressed pilot channel to transmission power ratio $\beta$=-8 dB, the number of complex delay profiles $N_{profile}$=32, and using these values, the error performance of DS/CDMA in Light shadowing environment was identical to the ideal QPSK error performance.

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