• Proceedings of the KIEE Conference
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• 2009.04b
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• pp.118-120
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• 2009

본 논문에서는 직접 전력변환방식의 단상 sag/swell 보상기를 구현하였다. 제안된 보상기는 정현파 입력/ 출력 필터, 직렬연결 변압기와 dc 링크 커패시터부가 없는 단상 back-to-back PWM컨버터로 구성되어 있다. 이 보상기의 장점은 dc-link 진해 커패시터가 제거되어 전력회로부가 간단하게 구현되어 향상된 신뢰성 및 내구성을 확인 할 수 있으며 동시에 단상 전압 sag/swell을 보상하며 스위칭 손실을 줄이는 간단한 PWM 방법을 들 수 있다. 더구나, 제안된 방법은 일반적인 직접 전력변환방식에서 요구되어지는 복잡한 4-step 전류 방법이 필요 없는 간단한 전류제어방법을 채용할 수 있는 구조이며 제안된 보상기의 구조와 PWM 방법의 타당성을 프로토타입 하드웨어를 제작하여 실험결과로 보상기의 우수성을 확인하였다.

• Journal of the Korean Institute of Illuminating and Electrical Installation Engineers
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• v.15 no.6
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• pp.65-72
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• 2001

This paper deals with a novel full digital control of the single-phase PWM(Pulse Width Modulation) inviter for UPS(Uninterruptible Power Supp1y). The voltage and current of output filter capacitor as a state variable are the feedback control input. In the proposed scheme a double deadbeat control consisting of minor current control loop and major voltage control loop have been developed In addition, a second order deadbeat currents control which should be exactly equal to its reference in two sampling time without error and overshoot is proposed to remove the influence of the calculation time delay. The load current prediction is achieved to compensate the load disturbance. The simulation and experimental result shows that the proposed system offers an output voltage with THD(Total Harmonic Distortion) less than 5% at a full nonlinear load.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2015.10a
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• pp.420-423
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• 2015

This paper proposes a method of non-linearity error detection and calibration for binary-weighted charge-driven DACs. In general, the non-linearity errors of DACs often occur due to the mismatch of layout designs or process variation, even when careful layout design methods and process calibration are adopted. Since such errors can substantially degrade the SNDR performance of DAC, it is crucial to accurately measure the errors and calibrate the design mismatches. The proposed method employs 2 identical DAC circuits. The 2 DACs are sweeped, respectively, by using 2 digital input counters with a fixed difference. A comparator identifies any non-linearity errors larger than an acceptable discrepancy. We also propose a calibration method that can fine-tune the DAC's capacitor sizes iteratively until the comparator finds no further errors. Simulations are presented, which show that the proposed method is effective to detect the non-linearity errors and calibrate the capacitor mismatches of a 12-bit DAC design of binary-weighted charge-driven structure.

• Journal of the Korean Institute of Telematics and Electronics C
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• v.35C no.12
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• pp.40-48
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• 1998

An offset compensation scheme for rail-to-rail CMOS op-amps with complementary input stages is presented. Two auxiliary amplifiers are used to compensate for the offsets of NMOS and PMOS differential input stages, and ping-pong control is employed for continuous-time operation. A 3V offset-compensated rail-to-rail CMOS op-amp has been designed and fabricated using a 0.8$\mu\textrm{m}$ single-poly, double-metal CMOS process. Measurement results show that offsets are reduced about 20 times by this scheme.

• Proceedings of the KIPE Conference
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• 2012.07a
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• pp.262-263
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• 2012

3상 새그 보상기는 계통 새그나 사고 발생 시 빠르게 이상상태를 검출하여 계통을 분리하고 수퍼커패시터에 충전된 에너지를 부하에 안정하고 연속적인 정격 전압을 공급하는 장치이다. 그러나 비선형 부하일 때, 3상 새그 보상기의 출력전압에 저차 고조파가 포함된 왜곡이 발생한다. 본 논문에서는 비선형 부하에서도 안정적인 정현파 전압을 공급하기 위해 선택적 고조파 제거 방식을 도입한 전압제어기를 제안 하였다. 새그 보상기 시작품을 제작하였으며, 제안한 선택적 고조파 제거 전압제어기의 타당성을 실험을 통하여 THD가 12.7%에서 4.3%로 개선되는 것을 확인하였다.

• The Transactions of the Korean Institute of Power Electronics
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• v.14 no.3
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• pp.188-196
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• 2009

Due to its high power density, long cycle life and clean nature supercapacitors are widely used for improving the dynamic characteristics of the new and renewable energy sources and extending the battery run-time and life. In this paper improved dynamic model of the supercapacitor is developed by the electrochemical impedance spectroscopy technique. The developed model can be used to accurately estimate the dynamic behaviour of the supercapacitor and calculate the exact capacitance value at a certain state of charges. The model of the supercapacitor in the frequency domain is equivalently transformed into that in the time domain for Matlab/Simulink simulaton. The simulation data shows fine agreements with experimental results, thereby proving the validity and the accuracy of the developed model.

• Journal of the Institute of Electronics and Information Engineers
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• v.50 no.12
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• pp.63-70
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• 2013

This paper describes a high PSRR low-dropout(LDO) linear regulator for wide frequency range without output-capacitor. Owing to both of the cascode compensation technique and the current buffer compensation technique in nested Miller compensation loop, the proposed LDO not only maintaines high stability but also achieves high PSRR over wide frequency range with reasonable on-chip capacitances. Since the external capacitor is removed by the proposed compensation techniques, the cost for pad is eliminated. The designed LDO works under the input voltage range from 2.5V to 4.5V and provides up to 10mA load current with the output voltage of 1.8V. The LDO was implemented with 0.18um CMOS technology and the area is 300um X 120 um. The measured power supply rejection ratio(PSRR) is -76dB and -43dB at DC and 1MHz, respectively. The operating current is 25uA.

• Proceedings of the KIPE Conference
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• 2013.11a
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• pp.75-76
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• 2013

최근 산업 및 경제의 급속한 발전으로 컴퓨터를 비롯한 전기 및 전자 장비, 통신기기, 반도체 장비 등 전기적 외란에 민감한 부하 설비의 사용이 급증하면서 전력 품질에 대한 관심이 고조되고 있다. 그 이유는 정밀 부하 장비들이 전압의 순간적 변동에 대하여 민감하여 이 문제로 인하여 파생되는 경제적 피해가 매우 크기 때문에 지속적인 관리가 필요하다. 이러한 문제 중에서 가장 빈번하게 발생하는 순간 전압 강하를 보상하기 위한 장치로 전기 이중 층 커패시터 (EDLC: Electric Double Layer Capacitor)를 에너지 저장장치로 사용한 순간전압강하 보상장치 (DVR: Dynamic Voltage Restorer) 시스템이 개발 되어 적용되고 있다. 본 논문에서는 현재 순간전압강하 보상장치에 사용되는 DVR 시스템에서 주로 사용되는 에너지 저장장치인 EDLC 보다 동일 사이즈 대비 에너지 밀도가 높은 하이브리드 커패시터를 적용하는 연구를 하고자 한다.

• Journal of the Institute of Electronics and Information Engineers
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• v.54 no.8
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• pp.107-114
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• 2017

In this paper, a novel power factor compensation system based on voltage-controlled method is proposed for 3-phase 4-wire power system. The proposed voltage-controlled power factor compensation system generates a reactive power required for compensation by applying a variable output voltage by a slidac to a capacitor. In conventional power factor compensation system using the capacitor bank method, the power factor compensation error occurs depending on the load condition due to the limited capacity of the capacitors. However, the proposed system compensates the power factor up to 100% without error. In this paper, we have developed a voltage-controlled power factor compensation system and a control algorithm for 3-phase 4-wire power system, and verify its performance through simulation and experiments. If the proposed power factor compensation system is applied to an industrial field, a power factor compensation performance can be maximized. As a result, it is possible to reduce of electricity prices, reduce of line loss, increase of load capacity, ensure the transmission margin capacity, and reduce the amount of power generation.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2006.05a
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• pp.906-909
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• 2006

This paper proposes a new body-effect compensated switch configuration for low voltage and low distortion switched-capacitor (SC) applications. The proposed circuit allows rail-to-rail switching operation for low voltage SC circuits and has better total harmonic distortion than the conventional bootstrapped circuit by 19 dB. A 2-1 cascaded sigma-delta modulator is provided for performing the high-resolution analog-to-digital conversion on audio codec in a communication transceiver. An experimental prototype for a single-stage folded-cascode operational amplifier (opamp) and a 2-1 cascaded sigma-delta modulator has been implemented in a 0.25 micron double-poly, triple-metal standard CMOS process with 2.7 V of supply voltage.