• Proceedings of the KIPE Conference
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• 2018.11a
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• pp.223-224
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• 2018

본 논문에서는 전기자동차용 저전압 배터리 충전기(Low-voltage DC-DC Converter, LDC)에 적합한 입력 직렬-출력 병렬 구조의 능동 클램프 포워드 컨버터의 모델링 및 제어기 설계를 제안한다. 제안하는 컨버터는 모든 스위치에서 소프트 스위칭을 성취하기 때문에 높은 효율을 달성할 수 있다. 또한 누설 인덕턴스의 영향을 포함한 컨버터의 정확한 소신호 모델을 통하여 모델링 기반의 제어기 설계를 제시한다. 제어기의 시뮬레이션 및 3.2kW급 시작품의 실험을 통하여 제안하는 컨버터의 성능을 검증하였다.

• Proceedings of the Acoustical Society of Korea Conference
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• spring
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• pp.339-342
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• 2000

본 논문에서는 DSP와 RISC 마이크로 콘트롤러의 결합으로 구성된 이중 코어 DSP를 이용하여 휴대장치에 적합한 저전력 MPEC-2 계층-III 복호화기의 구조를 제안하고 실시간 시스템을 구현하였다. 제안된 시스템은 디지털 오디오 데이터 처리부와 시스템 제어 정보처리부로 나누어 병렬처리가 가능한 구조이다. 디지털 오디오데이터 처리부에서는 DSP의 강력한 산술연산기능으로 MPEG 복호화 알고리듬을 수행하며 시스템 제어부에서는 마이크로 콘트롤러의 장점인 저가, 저전력의 제어 기능으로 사용자 인터페이스 및 파일 관리, 비트스트림 제어를 담당하도록 구성된다. 입력부에서는 Multi Meadia Card(MMC)를 지원하고, PC와 호환 가능하도록 파일 관리 시스템으로 운용되며 직렬 통신의 데이터 전송과 16비트 해상도 및 최대 48kHz 표본화주파수로 스테레오 출력이 가능하다. 구현된 시스템은 이중 코어를 이용하여 DSP의 연산량 및 동작속도의 감소로 인한 저가, 저전력의 효과로 인해 휴대장치에 적합하다.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.17 no.7 s.110
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• pp.673-683
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• 2006

In this paper, we investgate variation of phase and magnitude characteristics which become different as the variables of DGS are changed and propose the new method to easily decide the best optimum DGS pattern taking advantage of this trend. Generalized Chebyshev(GC) low pass filter(LPF) is designed by using DGS obtained from this method GC DGS LPF is more available for filter application than Chevyshev DGS LPF because GC LPF have parallel resonators as series circuits, therefore unlikely Chebyshev LPF, transform step of the series elements can be omitted. By using the proposed method, GC DGS LPF(N=5) and as a subject of comparison, conventional Chbyshev LPF(N=7) are designed and implementation. From the comparison of the measured data, we confirmed that the implemented GC DGS 5th order LPF have much better cutoff characteristics and reduce by 0.58 times size, on the other hand the stop bandwidth become widen about 1.57 times or more in comparison with the conventional Chevyshev 7th order LPF.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.22 no.1
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• pp.59-66
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• 2011

In this paper, a co-planar waveguide(CPW)-fed zeroth-order resonant(ZOR) antenna with an improved radiation efficiency was built and tested. The unit cell of the proposed antenna consists of a series metal-insulator-metal(MIM) capacitor and a shorted shunt stub inductor. In order to reduce the antenna size and to achieve the high radiation efficiency two shorted shunt stub arms bent by 90 degree were connected to the ground plane through the via. The proposed antenna consisting of two unit cells has an open ended composite right/left-handed(CRLH) transmission line structure. As a result the dominantly radiating parts of the antenna comes from shunt stub arms and vertical vias. The total size of the fabricated zeroth-order resonant antenna is $0.22\;{\lambda}_0{\times}0.22\;{\lambda}_0$. The measured gain and efficiency of the fabricated antenna have been enhanced by 3.07 dBi and 75 %, respectively, at the zeroth-order resonant frequency of 2.97 GHz.

• Journal of the Institute of Convergence Signal Processing
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• v.11 no.3
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• pp.244-249
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• 2010

The design of error correction code with low complexity has a good attraction for next generation multi-level cell flash memory. Sharing sub-expressions is effective method to reduce complexity and chip size. This paper proposes a new design method of m-bit parallel BCH encoder based on serial linear feedback shift register structure with low complexity using sub-expression. In addition, general algorithm for obtaining the sub-expression is introduced. The sub-expression can be expressed by matrix operation between sub-matrix of generator matrix and sum of two different variables. The number of the sub-expression is restricted by. The obtained sub-expressions can be shared for implementation of different m-parallel BCH encoder. This paper is not focused on solving a problem (delay) induced by numerous fan-out, but complexity reduction, expecially the number of gates.

• Journal of Korea Multimedia Society
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• v.3 no.5
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• pp.526-534
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• 2000

There have been many researches on the 3D graphic accelerator for high speed by needs of CAD/CAM,3D modeling, virtual reality or medical image. In this paper, an SIMD processor architecture for 3D graphic accelerator is proposed in order to improve the processing time of the 3D graphics, and a parallel Phong shading algorithm is presented to estimate performance of the proposed architecture. The proposed SIMD processor architecture for 3D graphic accelerator consists of PCI local bus interface, 16 Processing Elements (PE's), and Park's multi-access memory system (NAMS) that has 17 memory modules. A serial algorithm for Phong shading is modified for the architecture and the main key is to divide a polygon into $4\times{4}$ squares. And, for processing a square, 4 PE's are regarded as a PE Grou logically. Since MAMS can support block access type with interval 1, it is possible that 4 PE Groups process a square at a time. In consequence, 16 pixels are processed simultaneously. The proposed SIMD processor architecture is simulated by CADENCE Verilog-XL that is a package for the hardware simulation. With the same simulated results as that of the serial algorithm, the speed enhancement by the parallel algorithm to the serial one is 5.68.

• The Journal of The Korea Institute of Intelligent Transport Systems
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• v.8 no.4
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• pp.46-52
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• 2009

In this paper, a novel VCO (Voltage Controlled Oscillator) structure is proposed to achieve the characteristic of low phase noise and a wide frequency tuning range. The proposed scheme adopts an impedance transforming technique to change a series resonance into a parallel resonance for maximizing the susceptance slope parameter. The manufactured VCO shows a frequency tuning bandwidth of 600MHz from 10.1GHz to 10.7GHz with a tuning voltage varying from 0 to 9V, an excellent phase noise below -119dBc/Hz@1MHz offset. The harmonic suppression is measured above 28dB.

• Journal of the Institute of Electronics Engineers of Korea SC
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• v.37 no.2
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• pp.69-76
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• 2000

A dual-modulus prescaler divides the input signal by one of the moduli according to the control signal. In this paper, a new fast dual-modulus prescaler is proposed. The proposed prescaler has a ratioed-NOR structure different from a conventional ratioed-NAND structure. The proposed one can operate at a higher speed by using parallely connected NMOSs instead of using series-connected ones. HSPICE simulation results using HYUNDAI 0.65(m 2-poly 2-metal CMOS process parameters show that the maximum operating frequency of the proposed dual-modulus prescaler is 2.8㎓ with power consumption of 40.7㎽ at 5V supply voltage at $25^{\circ}C$. The proposed dual-modulus prescaler can be utilized for the frequency-synthesis in cellular radio front-ends.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.40 no.12
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• pp.80-86
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• 2003

Elliptic curve cryptosystem(ECC) offers the highest security per bit among the known publick key system. The benefit of smaller key size makes ECC particularly attractive for embedded applications since its implementation requires less memory and processing power. In this paper, we propose a new multiplier structure with configurable output sizes and operation cycles. The number of output bits can be freely chosen in the new architecture with the performance-area trade-off depending on the application. Using the architecture, a 193-bit normal basis multiplier and inversion unit are designed in GF(2$^{m}$ ). It is implemented using HDL and 0.35${\mu}{\textrm}{m}$ CMOS technology and the operation is verified by simulation.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.38C no.2
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• pp.196-201
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• 2013

In this paper, we proposed high speed LDPC encoder architecture for DVB-S2 standard. In conventional algorithm, the processes of parity calculations are serial fashion. Therefore conventional algorithm need clocks of number of parity. The proposed LDPC encoding architecture is based on a parallel 360 bits-wise operations. The key issues for realizing high speed are using the two kinds of index addresses and make use of memories efficiently. We implemented a half rate LDPC encoder on an FPGA, and confirmed its maximum throughput is up to 10 Gbps on 100MHz clock.