• Title/Summary/Keyword: 병렬 태스크

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A Method to Access Data for Spatial Operation in Parallel Distributed Processing System (병렬 분산 처리 시스템에서 공간 연산을 위한 데이터 접근 방안)

  • Kim, Jindeog
    • Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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    • 2016.10a
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    • pp.442-444
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    • 2016
  • 과거에 비해 비약적으로 생산되는 공간 데이터에 대한 처리를 위한 공간 연산은 빠른 처리 응답성을 요구하는 경우가 많다. 그래서 최근 하둡(Hadoop)과 같은 빅데이터 처리 시스템을 이용하여 처리하고자 하는 시도가 많다. 한편, 공간 조인은 데이터 분할(Partitioning)과 공간 색인의 이용 여부, 여과 단계와 정제 단계를 거치는 등 그 복잡도가 강한 공간 연산이다. 그래서 빅데이터 처리 시스템을 이용한 공간 조인의 처리 방식은 매우 다양하다. 그러나 지금까지 이러한 공간 조인의 처리 방식에 다른 리소스 활용에 대한 비교는 거의 없다. 이 논문에서는 다양한 공간 연산의 수행 방법에 따른 빅데이터 시스템 클러스터에서 데이터 전송 방식을 고찰하고 데이터 전송에 따른 네트워크 리소스의 효율적인 사용 방안을 제안하고자 한다. 구체적으로 단일할당과 다중할당 색인 기법의 비교, 파티셔닝 방법의 비교, 맵리듀스 시스템의 태스크 할당 방법에 따른 비교를 통해 다양한 연산 유형에 따른 공간 조인의 처리 방안 선정에 고려 요소를 제시하고자 한다.

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A Design of Industrial Controller with Multi-function and Multi-purpose (다기능 다목적을 갖는 산업용 제어기 설계)

  • 정보환;남진문
    • Journal of the Korea Computer Industry Society
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    • v.2 no.4
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    • pp.481-490
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    • 2001
  • In this paper, we propose the industrial controller with multi-function/multi-purpose in order to cope with a small-amount and large-items environments. The controller designed consists of Main Unit including all of information and Display Unit. The software in the Main Unit is composed of tasks and device drivers and each task is being processed in parallel by operating system supporting multitasking. The controller is structured in three levels to promptly address the control algorithm’s modification, MMI’s change, and so on. We can produce a controller without changing the first layer(hardware) and the second layer(firmware). We only modify the third layer(control algorithm) depending on control targets.

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A Partition Technique of UML-based Software Models for Multi-Processor Embedded Systems (멀티프로세서용 임베디드 시스템을 위한 UML 기반 소프트웨어 모델의 분할 기법)

  • Kim, Jong-Phil;Hong, Jang-Eui
    • The KIPS Transactions:PartD
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    • v.15D no.1
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    • pp.87-98
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    • 2008
  • In company with the demand of powerful processing units for embedded systems, the method to develop embedded software is also required to support the demand in new approach. In order to improve the resource utilization and system performance, software modeling techniques have to consider the features of hardware architecture. This paper proposes a partitioning technique of UML-based software models, which focus the generation of the allocatable software components into multiprocessor architecture. Our partitioning technique, at first, transforms UML models to CBCFGs(Constraint-Based Control Flow Graphs), and then slices the CBCFGs with consideration of parallelism and data dependency. We believe that our proposition gives practical applicability in the areas of platform specific modeling and performance estimation in model-driven embedded software development.

Performance Improvement for PVM by Zero-copy Mechanism (Zero-copy 기술을 이용한 PVM의 성능 개선)

  • 임성택;심재홍;최경희;정기현;김재훈;문성근
    • The Journal of Korean Institute of Communications and Information Sciences
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    • v.25 no.5B
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    • pp.899-912
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    • 2000
  • PVM provides users with a single image of high performance parallel computing machine by collecting machines distributed over a network. Low communication overhead is essential to effectively run applications on PVM based platforms. In the original PVM, three times of memory copies are required for a PVM task to send a message to a remote task, which results in performance degradation. We propose a zero-copy model using global shared memory that can be accessed by PVM tasks, PVM daemon, and network interface card(NIC). In the scheme, a task packs data into global shared memory, and notify daemon that the data is ready to be sent, then daemon routes the data to a remote task to which it is sent with no virtual data copy overhead. Experimental result reveals that the message round trip time between two machines is reduced significantly in the proposed zero-copy scheme.

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A GPU-enabled Face Detection System in the Hadoop Platform Considering Big Data for Images (이미지 빅데이터를 고려한 하둡 플랫폼 환경에서 GPU 기반의 얼굴 검출 시스템)

  • Bae, Yuseok;Park, Jongyoul
    • KIISE Transactions on Computing Practices
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    • v.22 no.1
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    • pp.20-25
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    • 2016
  • With the advent of the era of digital big data, the Hadoop platform has become widely used in various fields. However, the Hadoop MapReduce framework suffers from problems related to the increase of the name node's main memory and map tasks for the processing of large number of small files. In addition, a method for running C++-based tasks in the MapReduce framework is required in order to conjugate GPUs supporting hardware-based data parallelism in the MapReduce framework. Therefore, in this paper, we present a face detection system that generates a sequence file for images to process big data for images in the Hadoop platform. The system also deals with tasks for GPU-based face detection in the MapReduce framework using Hadoop Pipes. We demonstrate a performance increase of around 6.8-fold as compared to a single CPU process.

Adaptive Dynamic Load Balancing Strategies for Network-based Cluster Systems (네트워크 기반 클러스터 시스템을 위한 적응형 동적 부하균등 방법)

  • Jeong, Hun-Jin;Jeong, Jin-Ha;Choe, Sang-Bang
    • Journal of KIISE:Computer Systems and Theory
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    • v.28 no.11
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    • pp.549-560
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    • 2001
  • Cluster system provides attractive scalability in terms of compution power and memory size. With the advances in high speed computer network technology, cluster systems are becoming increasingly competitive compared to expensive MPPs (massively parallel processors). Load balancing is very important issue since an inappropriate scheduling of tasks cannot exploit the true potential of the system and can offset the gain from parallelization. In parallel processing program, it is difficult to predict the load of each task before running the program. Furthermore, tasks are interdependent each other in many ways. The dynamic load balancing algorithm, which evaluates each processor's load in runtime, partitions each task into the appropriate granularity and assigns them to processors in proportion to their performance in cluster systems. However, if the communication cost between processing nodes is expensive, it is not efficient for all nodes to attend load balancing process. In this paper, we restrict a processor that attend load balancing by the communication cost and the deviation of its load from the average. We simulate various models of the cluster system with parameters such as communication cost, node number, and range of workload value to compare existing load balancing methods with the proposed dynamic algorithms.

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Atomic Unit-based Post Editing for Hallucination Reduction (환각 현상 완화를 위한 단위 사실 기반 사후 교정)

  • Yonghwan Lee;Jeongwan Shin;Hyun-Je Song
    • Annual Conference on Human and Language Technology
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    • 2023.10a
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    • pp.222-227
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    • 2023
  • 환각 현상이란 LLM이 생성 태스크에서 사실이 아닌 내용을 생성하거나 근거가 없는 내용을 생성하는 현상을 말한다. 환각 현상은 LLM이 생성한 출력물에 대한 사용자의 신뢰를 떨어뜨리기 때문에 환각을 완화할 수 있는 방법이 필요하다. 최근 사후 편집 모델 중 하나인 RARR는 입력 텍스트를 질문들 순서에 따라 순차적으로 편집하여 환각을 완화하였지만 이전 단계의 편집 오류가 전파되거나 같은 작업을 반복하는 등의 단점이 있었다. 본 논문은 환각 현상 완화를 위한 단위 사실 기반 사후 교정을 제안한다. 제안한 방법은 입력 텍스트를 단위 사실로 분해하고 각 사실에 대응하는 질문을 생성한 후 검색된 관련 문서로 환각 여부를 판단한다. 환각이라 판단되면 편집을 수행하여 환각을 완화한다. 병렬적으로 편집을 진행하기 때문에 기존 연구의 순차적인 오류 전파 문제를 해결하고 기존 연구에 비해 더 빠른 사후 편집을 진행할 수 있다. 실험 결과, 제안 방법이 RARR보다 Preservation Score, 원문과의 사실성 일치여부, 의도 보존 여부에서 모두 우수한 성능을 보인다.

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Real-Time Multiprocessor Scheduling Algorithm using Neural Network and Its Hardware Design (신경망을 이용한 실시간 멀티프로세서 스케줄링 알고리즘과 하드웨어 설계)

  • Lee, Jae-Hyeong;Lee, Gang-Chang;Jo, Yong-Beom
    • Journal of the Institute of Electronics Engineers of Korea CI
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    • v.37 no.4
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    • pp.26-36
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    • 2000
  • This paper proposes a neural network algorithm for real-time multiprocessor scheduling problem. The proposed algorithm is developed base on Hopfield neural network for a benefit of parallel processing, in order to finish a requested task within a deadline time. To compare the performance of the proposed algorithm, we used EDA and LLA algorithm that has studied real-time multiprocessor scheduling before. The proposed algorithm is implemented hardware using VHDL.

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Static Analysis of AND-parallelism in Logic Programs based on Abstract Interpretation (추상해석법을 이용한 논리언어의 AND-병렬 태스크 추출 기법)

  • Kim, Hiecheol;Lee, Yong-Doo
    • Proceedings of the Korea Society for Industrial Systems Conference
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    • 1997.11a
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    • pp.79-89
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    • 1997
  • Logic programming has many advantages as a paradigm for parallel programming because it offers ease of programming while retaining high expressive power due to its declarative semantics. In parallel logic programming, one of the important issues is the compile-time parallelism detection. Static data-dependency analysis has been widely used to gather some information needed for the detection of AND-parallelism. However, the static data-dependency analysis cannot fully detect AND-parallelism because it does not provide some necessary functions such as the propagation of groundness. As an alternative approach, abstract interpretation provides a promising way to deal with AND-parallelism detection, while a full-blown abstract interpretation is not efficient in terms of computation since it inherently employs some complex operations not necessary for gathering the information on AND-parallelism. In this paper, we propose an abstract domain which can provide a precise and efficient way to use the abstract interpretation for the detection of AND-parallelism of logic programs.

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A Design of Real-Time Software Design Supporting System in CODARTS (CODARTS 방법론을 지원하는 실시간 S/W 설계 지원 시스템의 설계)

  • 우병찬;김규년
    • Proceedings of the Korean Information Science Society Conference
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    • 1998.10b
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    • pp.463-465
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    • 1998
  • COncurrent Design Approach for Real-Time System(이하 COSATRS) 방법론은 Gomaa가 제안한 실시간 설계 방법론으로서 Real-Time Structured Analysis(이하 RTSA)또는 Concurrent Object-Based Real-Time Analysis(이하 COBRA)방법론을 이용하여 Control and Data Flow Diagram(이하 C&DFD)를 구성하고 이것에 병렬 태스크 구조화 지침, 정보 은닉 모듈 구조화 지침을 적용하여 Task Architecture Diagram (이하 TDA), Information Hiding Module(이하 IHM)을 구성하고 나서 이 둘을 결합하여 Software Architecture Diagram(이하 SAD)를 구성하게 된다. 본 논문에서는 CODARTS 방법론의 적용과정을 테이블을 구성하여 적용함으로써 실시간 S/W 설계 지원 시스템을 설계하였다.