• Journal of the Korean Society for Railway
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• v.19 no.3
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• pp.314-323
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• 2016

Overhead line voltage of DC railway traction substations has rising or falling characteristics depending on the acceleration and regenerative braking of the subway train loads. The suppression of this irregular fluctuation of the line voltage gives rise to improved energy efficiency of both the railway substation and the trains. This paper presents parameter estimation schemes using the RC circuit model for an overhead line voltage at a 1500V DC electric railway traction substation. A linear artificial neural network with a back-propagation learning algorithm was trained using the measurement data for an overhead line voltage and four feeder currents. The least square estimation method was configured to implement batch processing of these measurement data. These estimation results have been presented and performance analysis has been achieved through raw data simulation.

• Journal of KIISE:Computer Systems and Theory
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• v.27 no.7
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• pp.639-649
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• 2000

In the relational database systems, the join operation is one of the most time-consuming query operations. Many parallel join algorithms have been developed to reduce the execution time. Multiple hash join algorithm using allocation tree is one of most efficient ones. However, it may have some delay on the processing each node of allocation tree, which is occurred in tuple-probing phase by the difference between one page reading time of outer relation and the processing time of already read one. In this paper, to solve the performance degrading problem by the delay, we develop a join algorithm using the concept of 'synchronization of page execution time' for multiple hash joins. We reduce the processing time of each nodes in the allocation tree and improve the total system performance. In addition, we analyze the performance by building the analytical cost model and verify the validity of it by various performance comparison with previous method.

• Transactions of the Korean Society of Mechanical Engineers
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• v.16 no.7
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• pp.1234-1243
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• 1992

A systematic procedure to design fuzzy PID controllers is developed in this paper. The concept of local fuzzy control cell is proposed by introducing both an adequate global control rule and membership functions to simplify a fuzzy logic controller. Fuzzy decision is made by using algebraic product and parallel firing arithematic mean, and a defuzzification strategy is adopted for improving the computational efficiency based on nonfuzzy micro-processor. A direct method, transforming the typical output of quasi-linear fuzzy operator to the digital compensator of PID form, is also proposed. Finally, the proposed algorithm is applied to an DC-servo motor. It is found that this algorithm is systematic and robust through computer simulations and implementation of controller using Intel 8097 micro-processor.

• The Transactions of the Korea Information Processing Society
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• v.4 no.1
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• pp.311-323
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• 1997

This paper presents a fast fault simulation system for detecting stuck-at faults in mixed-level combinational logic circuits with gale level and switch -level primitives. For a practical fault simulator, the types are not restricted to static switch-level and/or gate-level circuits, but include dynamic switch-level circuits. To efficiently handle the multiple signal contention problems at wired logic elements, we propose a six-valued logic system and its logic calculus which are used together with signal strength information. As a basic algorithm for the fault simulation process, a well -known gate-level parallel pattern single fault propagation(PPSFP) technique is extended to switch-level circuits in order to handle pass-transistor circuits and precharged logic circuits as well as static CMOS circuits. Finally, we demonstrate the efficiency of our system through the experimental results for switch-level ISCAS85 benchmark combinational circuits and various industrial mixed-level circuits.

• Journal of Astronomy and Space Sciences
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• v.24 no.2
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• pp.155-166
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• 2007

We have designed a high resolution proton and electron telescope for the detection of high energy particles, which constitute a major part of the space environment. The flux of the particles, in the satellite orbits, can vary abruptly according to the position and solar activities. In this study, a conceptual design of the detector, for adapting these variations with a high energy resolution, was made and the performance was estimated. In addition, a parallel processing algorithm was devised and embodied using FPGA for the high speed data processing, capable of detecting high flux without losing energy resolution, on board a satellite.

• The Transactions of the Korean Institute of Electrical Engineers A
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• v.54 no.8
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• pp.375-387
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• 2005

This paper presents an application of parallel Genetic Algorithm-Tabu Search (GA-TS) algorithm to search an optimal solution of a service restoration in distribution systems. The main objective of service restoration of distribution systems is, when a fault or overload occurs, to restore as much load as possible by transferring the do-energized load in the out of service area via network reconfiguration to the appropriate adjacent feeders at minimum operational cost without violating operating constraints, which is a combinatorial optimization problem. This problem has many constraints with many local minima to solve the optimal switch position. This paper develops parallel GA-TS algorithm for service restoration of distribution systems. In parallel GA-TS, GA operators are executed for each processor. To prevent solutions of low fitness from appearing in the next generation, strings below the average fitness are saved in the tabu list. If best fitness of the GA is not changed for several generations, TS operators are executed for the upper $10\%$ of the population to enhance the local searching capabilities. With migration operation, best string of each node is transferred to the neighboring node after predetermined iterations are executed. For parallel computing, we developed a PC cluster system consists of 8 PCs. Each PC employs the 2 GHz Pentium IV CPU and is connected with others through ethernet switch based fast ethernet. To show the validity of the proposed method, proposed algorithm has been tested with a practical distribution system in Korea. From the simulation results, we can find that the proposed algorithm is efficient for the distribution system service restoration in terms of the solution quality, speedup, efficiency and computation time.

• KIISE Transactions on Computing Practices
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• v.23 no.8
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• pp.466-472
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• 2017

Hardware Transactional Memory (HTM) has greatly changed the parallel programming paradigm for transaction processing. Since Intel has recently proposed Transactional Synchronization Extension (TSX), a number of studies based on HTM have been conducted. However, the existing studies support conflict prediction for a single cause of the transaction processing and provide a standardized TSX environment for all workloads. To solve the problems, we propose an efficient hardware transactional memory scheme for processing transactions in multi-core in-memory environment. First, the proposed scheme determines whether to use Software Transactional Memory (STM) or the serial execution as a fallback path of HTM by using a prediction matrix to collect the information of previously executed transactions. Second, the proposed scheme performs efficient transaction processing according to the characteristic of a given workload by providing a retry policy based on machine learning algorithms. Finally, through the experimental performance evaluation using Stanford transactional applications for multi-processing (STAMP), the proposed scheme shows 10~20% better performance than the existing schemes.

• The Transactions of the Korea Information Processing Society
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• v.5 no.1
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• pp.202-214
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• 1998

Exploitation of instruction-level parallelism(ILP) is an effective mechanism for improving the performance of modern super-scalar and VLIW processors. Various software techniques can be applied to increase ILP. Among these techniques, predicated execution is the one that increases the degree of ILP by allowing instructions from different basic blocks to be converted to a single basic block by removing branch instructions. In this paper, a global predicate-sensitive scheduling algorithm is proposed to improve the performance for ILP processors that support predicated execution. In order to examine the performance of proposed algorithm, a C compiler and a simulator are developed. By simulating various benchmark programs with the compiler and the simulator, the performance results of this algorithm are measured and the effectiveness of the algorithm is verified. As a result of measure performance with I, 2, 4 issue execution, this study was confirmed average performance by 20% or more.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.37B no.9
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• pp.814-821
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• 2012

We propose a network processor called an OmniFlow processor capable of wire-speed flow management by a hardware-based flow admission control(FAC) in this paper. Because the OmniFlow processor can set up and release a wire-speed connection for flows, the update period of flows can be set to a short time, and only active flows can be effectively managed by terminating a flow that does not have a packet transmitted within this period. Therefore, the FAC can be used to provide a reliable transmission of UDP as well as TCP applications. This processor is fabricated in 65nm CMOS technology, and total gate count is 25 million. It has 40 Gb/s throughput performance in using the 32 RISC cores when maximum operating frequency is 555MHz.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.32 no.5A
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• pp.460-466
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• 2007

There are two coordination functions in IEEE 802.11 standard. One is PCF, polling based function, and the other is DCF, contention based function. DCF is simpler than PCF but the performance is similar with the latter. That's the reason why DCF is more popular than PCF. However, DCF has a risk of collision with other nodes in the network because the function is a distributed contention based one. CSMA/CA of DCF has collision avoidance algorithm in it, but the performance of avoidance algorithm has limitations. In this paper we proposed a new scheme called TAR(Tone-based Access scheme with Repetitive conention). In TAR, there is narrow contention-only channel other than original data transmitting channel, so that both a data transmission and the contention can be performed simultaneously. The TAR uses the same contention concept with the CSMA/CA, but it has the originality for the narrow contention channel and the repetitive contention scheme which greatly reduce the collision probability. We proved the performance of TAR by some simulations, and it showed good results.