• Title/Summary/Keyword: 병렬 시뮬레이션

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The bidirectional DC module type PCS design for the System Inter Connection PV-ESS of Secure to Expandability (계통 연계 PV-ESS 확장성 확보를 위한 병렬 DC-모듈형 PCS 설계)

  • Hwang, Lark-Hoon;Na, Seung-Kwon;Choi, Byung-Sang
    • The Journal of Korea Institute of Information, Electronics, and Communication Technology
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    • v.14 no.1
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    • pp.56-69
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    • 2021
  • In this paper, the PV system with a link to the commercial system needs some advantages like small capacity, high power factor, high reliability, low harmonic output, maximum power operation of solar cell, and low cost, etc. as well as the properties of inverter. To transfer the PV energy of photovoltaic power generation system to the system and load, it requires PCS in both directions. The purpose of this paper is to confirm the stable power supply through the load leveling by presenting the PCS considering ESS of photovoltaic power generation. In order to achieve these purpose, 5 step process of operation mode algorithm were used according to the solar insolation amount and load capacity and the controller for charging/ discharging control was designed. For bidirectional and effective energy transfer, the bidirectional converter and battery at DC-link stage were connected and the DC-link voltage and inverter output voltage through the interactive inverter were controlled. In order to prove the validity of the suggested system, the simulation using PSIM was performed and were reviewed for its validity and stability. The 3[kW] PCS was manufactured and its test was conducted in order to check this situation. In addition, the system characteristics suggested through the test results was verified and the PCS system presented in this study was excellent and stronger than that of before system.

Performance Analysis of Slave-Side Arbitration Schemes for the Multi-Layer AHB BusMatrix (ML-AHB 버스 매트릭스를 위한 슬레이브 중심 중재 방식의 성능 분석)

  • Hwang, Soo-Yun;Park, Hyeong-Jun;Jhang, Kyoung-Son
    • Journal of KIISE:Computer Systems and Theory
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    • v.34 no.5_6
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    • pp.257-266
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    • 2007
  • In On-Chip bus, the arbitration scheme is one of the critical factors that decide the overall system performance. The arbitration scheme used in traditional shared bus is the master-side arbitration based on the request and grant signals between multiple masters and single arbiter. In the case of the master-side arbitration, only one master and one slave can transfer the data at a time. Therefore the throughput of total bus system and the utilization of resources are decreased in the master-side arbitration. However in the slave-side arbitration, there is an arbiter at each slave port and the master just starts a transaction and waits for the slave response to proceed to the next transfer. Thus, the unit of arbitration can be a transaction or a transfer. Besides the throughput of total bus system and the utilization of resources are increased since the multiple masters can simultaneously perform transfers with independent slaves. In this paper, we implement and analyze the arbitration schemes for the Multi-Layer AHB BusMatrix based on the slave-side arbitration. We implement the slave-side arbitration schemes based on fixed priority, round robin and dynamic priority and accomplish the performance simulation to compare and analyze the performance of each arbitration scheme according to the characteristics of the master and slave. With the performance simulation, we observed that when there are few masters on critical path in a bus system, the arbitration scheme based on dynamic priority shows the maximum performance and in other cases, the arbitration scheme based on round robin shows the highest performance. In addition, the arbitration scheme with transaction based multiplexing shows higher performance than the same arbitration scheme with single transfer based switching in an application with frequent accesses to the long latency devices or memories such as SDRAM. The improvements of the arbitration scheme with transaction based multiplexing are 26%, 42% and 51%, respectively when the latency times of SDRAM are 1, 2 and 3 clock cycles.