• Title/Summary/Keyword: 병렬코아

Search Result 6, Processing Time 0.019 seconds

Forces and Displacements of Outrigger-Braced Structures with a Pair of Coupled Cores (병렬코아를 갖는 아웃리거구조물의 응력과 변위)

  • 정동조;이태희
    • Journal of the Computational Structural Engineering Institute of Korea
    • /
    • v.16 no.3
    • /
    • pp.291-299
    • /
    • 2003
  • Based on the continuum approach, an investigation is made to get the forces and displacements of laterally loaded outrigger braced structures with a pair of coupled cores, and to show the effect of stiffening outriggers on the behavior of the structure. From the condition that the rotation of the core at the outrigger level is matched with the rotation of the corresponding outrigger, the outrigger restraining moment is derived analytically. From this, the core moment diagram, the column axial forces, and the horizontal displacements of the structure may be determined. Comparisons with the results by the program MIDAS-GEN for the structural models, have shown that this analysis can give reasonably accurate results for outrigger-braced structures with a pair of coupled cores. And a lateral displacement at the top of the structure is influenced by the outrigger location than the core location. Although the formulae are accurate only for idealized outrigger braced structures, they have a useful practical purpose in providing a guide to the behavior, and for making approximate estimates of the forces and displacements, in practical outrigger braced structures with a pair of coupled cores.

Design of X-band Core Chip Using 0.25-㎛ GaAs pHEMT Process (0.25 ㎛ GaAs pHEMT 공정을 이용한 X-대역 코아-칩의 설계)

  • Kim, Dong-Seok;Lee, Chang-Dae;Lee, Dong-Hyun;Yeom, Kyung-Whan
    • The Journal of Korean Institute of Electromagnetic Engineering and Science
    • /
    • v.29 no.5
    • /
    • pp.336-343
    • /
    • 2018
  • We herein present the design and fabrication of a Rx core chip operating in the X-band (10.5~13 GHz) using Win's commercial $0.25-{\mu}m$ GaAs pHEMT process technology. The X-band core chip comprises a low-noise amplifier, a four-bit phase shifter, and a serial-to-parallel data converter. The size is $1.75mm{\times}1.75mm$, which is the state-of-the-art size. The gain and noise figure are more than 10 dB but less than 2 dB, and both the input and output return losses are less than 10 dB. The RMS phase error is less than $5^{\circ}$, and the P1dB is 2 dBm at 12.5 GHz, the performance of which is equivalent to other GaAs core chips. The fabricated core chip was packaged in a QFN package type with a size of $3mm{\times}3mm$ for the convenience of assembly. We confirmed that the performance of the packaged core chip was almost the same as that of the chip itself.

Construction of a Fluxgate Magnetometer for the Measurment of Magnetic Field Difference (자기장 차이 측정용 플럭스게이트 마그네토미터 제작)

  • Choi, K.W.;Son, D.;Cho, Y.
    • Journal of the Korean Magnetics Society
    • /
    • v.5 no.4
    • /
    • pp.304-308
    • /
    • 1995
  • In order to measure magnetic field difference, we have constructed a fluxgate magnetometer which is based on the measurement of apparent coreci ve field strength from the magnetizing current of two sensors. 'Co-based amorphous ribbon, which has square shape of ac hysteresis loop, was used as core material. Two sensors have 315 turns of the primary and the secondary windings respectively, and core size of 2 mm wide and 30 mm long. The primary windings are connected parallel to measure external magnetic field difference and the secondary windings serieally for the averaged magnetic induction of the cores. The constructed magnetometer could measure magnetic field difference with sensitivity of $1.6{\times}10^{6}V/T$ and resolution of 1 nT at 1 Hz bandwidth.

  • PDF

Design of a Serial-to-Parallel Converter Using GaAs pHEMT (GaAs pHEMT를 이용한 직-병렬변환기 설계)

  • Lee, Chang-Dae;Lee, Dong-Hyun;Yeom, Kyung-Whan
    • The Journal of Korean Institute of Electromagnetic Engineering and Science
    • /
    • v.29 no.3
    • /
    • pp.171-183
    • /
    • 2018
  • Herein, we show the design and fabrication of a serial-to-parallel converter (SPC) using the $0.25-{\mu}m$ GaAs pHEMT process. The serial-to-parallel converter is composed of four bits to control the four phase shifters used in the core chip. The SPC stores the received serial data signal to a register in the SPC and converts the stored data into the parallel data. Each converted output data can control four phase shifters. The size of the fabricated SPC is $1,200{\times}480{\mu}m^2$ and it uses two DC power supplies of 5 V and -3 V. The consumption current of each DC power supply is 7.1 mA for 5 V, and 2.1 mA for -3 V.

Low Power Digital Servo Architecture for Optical Disc (광디스크 디지털 서보의 저전력 구현 아키텍쳐)

  • Huh, Jun-Ho;Kim, Soo-Won
    • Journal of the Institute of Electronics Engineers of Korea SC
    • /
    • v.38 no.2
    • /
    • pp.31-37
    • /
    • 2001
  • Digital servo implementation in optical servo chip has been spotlighted since it is easy to integrate with other blocks and it has less sensitive characteristics change in terms of temperature variation and better flexibility to the system variation like pick-up. Therefore, Optical disc players adopted digital servo are increasing in market. However, one drawback of digital signal processor embedded digital servo is power consumption that is one of the most important factors of portable optical disc player system. For that reason, this paper introduces new architecture to reduce power consumption of digital servo by means of reducing DSP load but increasing minimum hardware size. The main idea of reducing power consumption of digital servo greatly is utilizing CDP characteristics as most operations are done and used up most operating steps of DSP at the initial time, but most power consumption is occurred in play mode. Therefore, if operating steps for digital filtering in play mode could be reduced greatly, power consumption of overall system can be reduced greatly. This paper shows an example that low power digital servo architecture whose current is reduced almost 83%, compare to that of digital servo which is not applied by the low power architecture introduced in this paper.

  • PDF

Three-Phase ZVS DC-DC Converter with Low Transformer Turn Ratio for High Step-up and High Power Applications (낮은 변압기 턴비를 갖는 고승압.대전력용 3상 ZVS DC-DC컨버터)

  • Kim, Joon-Geun;Park, Chan-Soo;Choi, Se-Wan;Park, Ga-Woo
    • The Transactions of the Korean Institute of Power Electronics
    • /
    • v.16 no.3
    • /
    • pp.242-249
    • /
    • 2011
  • The proposed converter has easy device selection for high step-up and high power applications since boost half bridge and voltage doubler cells are connected, respectively, in parallel and series in order to increase output power and voltage. Especially, optimized design of high frequency transformers is possible owing to reduced turn ratio and eliminated dc offset, and distributed power through three cores is beneficial to low profile and thermal distribution. The proposed converter does not necessitate start-up circuit and additional clamp circuit due to the use of whole duty range between 0 and 1 and is suitable for applications with wide input voltage range. Also, high efficiency can be achieved since ZVS turn on of switches are achieved in wide duty cycle range and ZCS turn on and off of diodes are achieved. The proposed converter was validated through 5 kW prototype.