• Electronics and Telecommunications Trends
• /
• v.14 no.1 s.55
• /
• pp.1-12
• /
• 1999

고성능 프로세서와 초고속 네트워크 등의 하드웨어 기술이 발전하게 됨에 따라 최근 슈퍼컴퓨터와 같은 고가의 대형 컴퓨터를 사용하는 대신에 여러 개의 프로세싱 노드들을 클러스터링 기술을 사용하여 고속의 네트워크로 묶는 클러스터 시스템을 많이 활용하고 있다. 클러스터 시스템의 응용 분야는 병렬 처리를 비롯하여 멀티미디어나 대용량 데이터 베이스와 같은 입출력 중심적인 분야까지 넓어지게 되었다. 본 고에서는 클러스터 시스템을 구축하기 위하여 필요한 전반적인 클러스터 컴퓨팅 기술에 대하여 설명하였다.

• Proceedings of the KAIS Fall Conference
• /
• 2004.11a
• /
• pp.174-178
• /
• 2004

본 논문에서는 일명 델타변환 무정전전원장치(UPS)로서 알려져 있는 3상 라인 인터랙티브 UPS 시스템의 성능 시험에 대해서 다루고 있다. 델타변환 UPS는 종래의 단일 변환 라인 인터랙티브 UPS 시스템에서 직렬 인덕터를 제거하고 직렬 및 병렬 PWM 컨버터를 사용하는 새로운 라인 인터랙티브 UPS 시스템으로 전원 전류를 직접 제어함으로써 UPS 시스템의 입출력 특성들이 상당히 개선되는 것으로 알려져 있다. 여기서는 UPS 시스템의 성능 시험에서 중요한 내용들인 부하시험, 정전/복전시험, 동기절체 시험 등에 대한 결과들을 제시하고 델타변환 UPS 시스템에 대한 전반적인 평가를 한다.

• Proceedings of the Korea Multimedia Society Conference
• /
• 2002.05c
• /
• pp.49-53
• /
• 2002

본 논문은 광학 현미경으로 관찰된 데이터들을 분산 시스템이나 병렬 시스템에 구현한 소프트웨어 시스템의 설계에 대한 것으로, 이 시스템이 처리하는 데이터들이 대용량이라는 특성과 함께 다중 해상도의 특성을 갖는다. 본 시스템은 고객/서버 모델을 기반으로 하였으며, 대용량 데이터 처리시 성능에 중요한 디스크 입출력의 대역폭을 높이기 위해 힐버트 곡선 기반의 분산 알고리즘을 적용하였다. 서버부는 조정자 노드와 서비스 노드로 구성되며, 시스템의 제 구성 요소들간에는 정해진 통신 규약에 따라 메시지를 주고 받고, 상호 독립적이다. 이 시스템은 의학 교육, 원격 병리, 가상 학술 회의 등에 응용될 때 활용 가치가 높을 것으로 기대된다.

• Proceedings of the Korea Information Processing Society Conference
• /
• 2013.05a
• /
• pp.41-44
• /
• 2013

병렬 및 분산 컴퓨팅 영역에서 기존 실험의 대부분은 속도 개선만을 고려하여 알고리즘을 설계 하였다. 이 연구는 일정 수준의 속도 개선을 보이면서도 에너지 절감효과를 기대하고자 저장장치 및 캐쉬의 활용을 생각하여 알고리즘을 설계하는 연구를 진행 한다. 이를 보이기 위해 입출력 비중이 높은 경우를 대표하는 외부 정렬 실험과 순수 연산의 비중이 높은 경우를 대표하는 매트릭스 실험을 하였다. 연구 결과를 통해 저장장치 및 캐쉬를 고려한 알고리즘이 그린 컴퓨팅에 이바지 할 수 있다는 것을 말하고자 한다.

• Journal of KIISE
• /
• v.44 no.5
• /
• pp.469-475
• /
• 2017

The emerging NVMe-based multi-queue SSDs provides a high bandwidth by parallel I/O, i.e., each core performs I/O through its dedicated queue in parallel with other cores. To provide a bandwidth share for each application with I/O, a fair-share scheduler that provides a bandwidth share to each core is required. In this study, we proposed a multi-core scalable fair-queuing algorithm for multi-queue SSDs. The algorithm adopts randomization to minimize the inter-core synchronization overheads and provides a weight-proportional bandwidth share to each core. The results of our experiments indicated that the proposed algorithm gives accurate bandwidth partitioning and outperforms the existing FlashFQ scheduler, regardless of the number of cores for a Linux kernel with block-mq.

• Journal of the Institute of Electronics Engineers of Korea SD
• /
• v.48 no.8
• /
• pp.45-52
• /
• 2011

Flash memory is becoming widely prevalent in various area due to high performance, non-volatile features, low power, and robust durability. As price-per-bit is decreased, NAND flash based SSDs (Solid State Disk) have been attracting attention as the next generation storage device, which can replace HDDs (Hard Disk Drive) which have mechanical properties. Especially for the single package SSD, if channel number or FIFO buffer size per channel increases to improve performance, the size of a controller and I/O pin count will increase linearly with channel numbers and form factor will be affected. We propose a novel technique which can minimize form factor by optimizing the number of NAND flash channels and the size of interface FIFO buffer in the SSD. For SSD with 10 channel and double buffer, the experimental results show that buffer block size can be reduced about 73% without performance degradation and total size of a controller can be reduced about 40% because control block per channel and I/O pin count decrease according to decrease channel number.

• The Journal of the Korea institute of electronic communication sciences
• /
• v.7 no.6
• /
• pp.1429-1435
• /
• 2012

DC-DC converter commonly used in photovoltaic systems, fuel cell systems and electric vehicles is a boost converter. The interleaved boost converter, connected in parallel by several boost converters and operated by the phase difference to reduce the input and output current ripple, has been widely used in recent years. Because of small input and output current ripples, the circuit can reduce the size of the input and output capacitors. Thus, instead of conventional electrolytic capacitor, the film capacitor with high reliability can be used and this is the life and reliability of the entire system can be improved. In this paper, the output current ripple formulas of the multi-stage interleaved boost converter are derived, and the characteristics in accordance with duty are found out. In order to verify the abovementioned contents, the derived results will make a comparison with the calculated values by using PSIM tool.

• The Transactions of the Korea Information Processing Society
• /
• v.3 no.3
• /
• pp.617-630
• /
• 1996

In this paper, a shared-concurrent file system (S-CFS) is designed and implemented using conventional disks as disk arrays on a Workstation Cluster which can be used as a small-scale server. Since it is implemented on UNIX operating systems, S_CFS is not only portable and flexible but also efficient in resource usage because it does not require additional I/O nodes. The result of the research shows that on small-scale systems with enough disks, the performance of the concurrent file system on transaction processing applications is bounded by the bottleneck of CPUs computing powers while the performance of the concurrent file system on massive data I/Os is bounded by the time required to copy data between buffers. The concurrent file system,which has been implemented on a Workstation Cluster with 8 disks,shows a throughput of 388 tps in case of transaction processing applications and can provide the bandwidth of 15.8 Mbytes/sec in case of massive data processing applications. Moreover,the concurrent file system has been dsigned to enhance the throughput of applications requirring high performance I/O by controlling the paralleism of the concurrent file system on user's side.

• The Transactions of the Korean Institute of Power Electronics
• /
• v.3 no.4
• /
• pp.353-364
• /
• 1998

This paper presents a systematic approach to the modeling of power electronic circuits with systemlongrightarrowlevel simulation l languages. It is shown that a circuit model reduces to one of four basic types according to input/output conditions. The e elementary models for single series components and shunt components are derived which are integrated to develop a m model of given converter circuit. The constraints imposed on the model development-matching input/output conditions a and avoiding algebraic loop-are discussed in relation to the realization example of a buck converter circuit model. It is s shown that the constraints can always be fullfilled by introducing fictitious interface blocks, which is generalized to the c concept of model transformation.

• The Transactions of the Korea Information Processing Society
• /
• v.2 no.3
• /
• pp.433-442
• /
• 1995

This paper presents an improved VLSI implementation of a parallel sorter to achieve O(Ν) time complexity. Many fast VLSI sort algorithms have been proposed for sorting N elements in O(log Ν) time. However, most such algorithms proposed have complex network structure without considering data input and output time. They are also very difficult to expand or to use in real applications. After analyzing the chip area and time complexity of several parallel sort algorithms with overlapping data input and output time, the most effective algorithm, the rebound sort algorithm, is implemented in VLSI with some improvements. To achieve O(Ν) time complexity, an improved rebound sorter is able to sort 8 16-bits records on a chip. And it is possible to sort more than 8 records by connecting chips in a chain vertically.