• Journal of IKEEE
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• v.22 no.3
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• pp.882-885
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• 2018

Recently, signal integrity on PCB (printed circuit board) becomes very important as the system operation speed increases. So far, PCB is customarily designed to minimize area and cost. However, ultra-high-speed PCB often fail to operate properly, unless it is precisely and carefully designed considering dielectric characteristics, line width, line spacing, and impedance matching. This paper surveys many problems in ultra-high-speed PCB and various design methods to mitigate them.

• The Journal of the Korea institute of electronic communication sciences
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• v.14 no.2
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• pp.289-296
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• 2019

Recently, the development of smartphone camera technology enables to shoot high quality video. In order to utilize these techniques in various ways, it is necessary to be able to transmit signals to an external device such as a external display. The transmission performance of the video signal is determined by the loss of the transmission line and the length of the wiring. In this paper, we propose the HDMI transmission line design criterion according to the wiring length changed according to the smartphone design and the surface roughness amplitude of the printed circuit board conductor wiring material. Also, we verified the proposed design criteria for the actual smartphone design. The proposed design criterion can be applied to various application fields including high-speed signal transmission line besides mobile application.

• Journal of the Institute of Convergence Signal Processing
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• v.4 no.1
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• pp.64-70
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• 2003

Current growth of VLSI design depends critically on the research and development (If automatic layout tool. Automatic layout is composed of placement assigning a specific shape to a block and arranging the block on the layout surface and routing finding the interconnection of all the nets. Algorithms Performing placement and routing impact on Performance and area of VLSI design. Channel routing is a problem assigning each net to a track after global routing and minimizing the track that assigned each net. In this paper we propose a genetic algorithm searching solution space for the netlist partitioning problem for 4-layer channel routing. We compare the performance of proposed genetic algorithm(GA) for channel routing with that of simulated annealing(SA) algorithm by analyzing the results which are the solution of given problems. Consequently experimental results show that out proposed algorithm reduce area over the SA algorithm.

• Review of KIISC
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• v.14 no.2
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• pp.78-88
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• 2004

정보 통신과 반도체 공정 기술의 급격한 발전으로 나노기술이 가까운 시일 내에 실용화되고, 유비쿼터스 환경이 도래할 것으로 예측된다. 나노기술 환경에서 사용되는 디바이스의 고집적도, 낮은 구동 능력, 배선 제약 특성이 정보 보호 분야에 사용되는 프로세서 구조와 회로 설계 기술을 크게 바꿀 것으로 예측된다. 본 연구에서는 이러한 기술 변혁에 대비하기 위해 나노기술 환경에 적합한 차세대 정보 보호 프로세서 구조와 회로 설계 기술을 분석하였다.

• Journal of the Korean Institute of Telematics and Electronics D
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• v.35D no.10
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• pp.67-75
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• 1998

This paper examined the geometrical variables of microstrip to control the characteristic impedance of MCM interconnect and also with respect to the practical requirements, evaluated the critical lengths for attenuation, propagation delay, and crosstalk at 500 MHz frequency compared to at 50 MHz frequency. With the illustration of each MCM-L and MCM-D interconnect having 50 characteristic impedance, it was revealed that the most important geometrical variables to control the characteristic impedance of microstrip are eventually dielectric thickness and line width. In particular, the dielectric thickness of MCM-D interconnect must be controlled with tolerance below 2 m. It is clear that the attenuation does not give rise to signal distortion in the range of up to 500MHz frequency for both MCM-L and MCM-D interconnects. However, the propagation delay is so significant that both MCM-L and MCM-D interconnects should be matched with load at the 500 MHz frequency. For the MCM-D interconnect, the crosstalk voltage would not be high to generate the wrong signal on the neighboring line at 500 MHz frequency, but the MCM-L interconnect could not be used due to severe crosstalk. Eventually, it is clear that the transmission line behavior must be studied for the design of MCM substrate at the 500 MHz frequency.

• Journal of the Institute of Electronics and Information Engineers
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• v.51 no.10
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• pp.228-234
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• 2014

In the case of construction equipment, internal wiring has a very complicated structure such as an electrical wiring and hydraulic equipments. Because of these complex wiring, a lot of time is spent on maintenance and equipment manufacturing. In this paper, we design and implementation of the high-reliability PLC(Power Line Communication) -CAN(Controller Area Network) communication module to reduce electrical wiring of the construction equipment.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.16 no.1
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• pp.13-22
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• 1991

In this paper we designed 2 bit ECC(Error Checking and Correction) circuit using Single Layer Perceptron type neural networks. We used (11, 6) block codes having 6 data bits and 8 check bits with appling cyclic hamming codes. All of the circuits are layouted by CMOs 2um double metal design rules. In the result of circuit simulation, 2 bit ECC circuit operates at 67MHz of input frequency.

• Journal of Korea Society of Industrial Information Systems
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• v.19 no.6
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• pp.33-41
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• 2014

In this paper, we propose a D flip-flop based on quantum-dot cellular automata(QCA) clocking and design a programmable quantum-dot cell(QPCA) structure using the proposed D flip-flop. Previous D flip-flops on QCA are that input should be set to an arbitrary value, and wasted output values exist because it was utilized to duplicate by clock pulse and QCA clocking. In order to eliminate these defects, we propose a D flip-flop structure using binary wire and clocking technique on QCA. QPCA structure consists of wire control logic, rule control logic, D flip-flop and XOR logic gate. In experiment, we perform the simulation of QPCA structure using QCADesigner. As the result, we confirm the efficiency of the proposed structure.

• Proceedings of the Optical Society of Korea Conference
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• 2003.07a
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• pp.206-207
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• 2003

광집적회로의 등장으로 그 설계에 있어서 다양한 구조의 광배선은 필수적 요소가 되었다. 일반적으로 전기적 배선 및 소자간에 전자기파의 간섭으로 인해 신호의 왜곡이 야기될 뿐 아니라 기생정전효과 등에 의해 소자 시간지연이 유발되듯이, 광 집적회로에서도 광배선간 감쇄필드의 겹침으로 인해 원하지 않는 광결합이 발생하게 된다. 이러한 광집적회로내에서의 이러한 불필요한 광결합을 줄이기 위해서 곡선형 구조의 광배선들이 이용되며 대부분의 경우 이러한 곡선형 도파로 부분의 광결합은 무시된다. (중략)

• Journal of the Institute of Electronics Engineers of Korea SC
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• v.39 no.2
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• pp.146-156
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• 2002

In this paper, a new virtual-straight line parameter determination methodology and fast time domain simulation technique for non-uniform interconnects are presented and verified. Time domain signal response of interconnects circuit considering the characteristic of non-linear transistor is performed by using model order reduction method. Since model order reduction method is peformed by using per unit length parameters, virtual- straight line parameters for non-uniform interconnects are determined. Its method is integrated into Berkeley SPICE and shown that time domain signal responses using proposed method have a good agreement with the results of conventional circuit simulator HSPICE. The proposed method can be efficiently employed in the high-performance VLSI circuit design since it can provide a fast and accurate time domain signal response of complicated multi - layer interconnects.