• Journal of the Korean Institute of Telematics and Electronics S
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• v.36S no.5
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• pp.12-20
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• 1999

본 논문에서는 DVB-T (digital video broadcasting-terrestrial) 수신기의 동기화 알고리듬과 각 동기단 사이의 연동 알고리듬을 제안한다. OFDM( orthohonal frequency division multiplexing) 수신단에서는 프레임 동기, 반송파 동기, 심볼 타이밍 동기가 요구되어진다. 기존의 반송파 동기 방법은 부반송파 간격의 정수배 주파수 옵셋 보상 후 잔존해 있는 주파수 옵셋이 -0.5×(부반송파 간격) 혹은 +0.5×(부반송파 간격)에 가까운 값을 가질 때 많은 시간이 소요되는 문제점을 가지고 있다. 본 논문에서는 시스템의 복잡도를 그대로 유지 하면서 초기 동기화 시간을 줄일 수 있는 반송파 동기 알고리듬을 제안한다. 그리고 DVB-T모드를 추정하는 알고리듬을 제안하고 반송파 동기 추적루프와 심볼 타이밍 동기 추적루프를 동시에 동작시킴으로써 초기 동기화 시간을 추가적으로 줄일 수 있는 심볼 타이ALD 동기 알고리듬을 제안한다. 그리고 전체 수신기 모델의 연동 방안을 제시한다.

• Journal of Korea Society of Industrial Information Systems
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• v.8 no.1
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• pp.83-91
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• 2003

High-speed QPSK demodulator has been in important design objective of any wireless communication systems, especially those offering broadband multimedia service. This paper describes all-digital QPSK demodulator for high-speed wireless communications, and its hardware structures are discussed. All-digital QPSK demodulator is mainly composed of symbol time circuit and carrier recovery circuit to estimate timing and phase-offsets. There are various schemes. Among them, we use Gardner algorithm and Decision-Directed carrier recovery algorithm which is most efficient scheme to warrant the fast acquisition and tacking to fabricate FPGA chip. The testing results of the implemented onto CPLD-EPF10K100GC 503-4 chip show demodulation speed is reached up to 2.6[Mbps]. If it is implemented a CPLD chip with speed grade 1, the demodulation speed can be faster by about 5 times. Actually in case of designing by ASIC, its speed my be faster than CPLD by 5 times. Therefore, it is possible to fabricate the all-digital QPSK demodulator chipset with speed of 50[Mbps].

• The Journal of Korean Institute of Communications and Information Sciences
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• v.31 no.7C
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• pp.706-712
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• 2006

In this letter, we propose a compact CORDIC processor for implementation of carrier frequency synchronization block in an OFDM (Orthogonal Frequency Division Multiplexing) system. The compact CORDIC processor is proposed by using inherenct properties of an OFDM system for estimation and compensation of carrier frequency offset, and is composed of a compact CORDIC preprocessor and a compact CORDIC processor. The compact CORDIC preprocessor plays a role of normalizing input signal efficiently, and the compact CORDIC processor is proposed to perform the vectoring mode and rotational mode jointly in CORDIC operation for carrier frequency synchronization. It is shown by FPGA implementation that the proposed compact CORDIC processor can achieve better performance with a significantly reduced hardware complexity than the conventional CORDIC approach.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.14 no.12
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• pp.1248-1255
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• 2003

High-speed QPSK demodulator has been one important design objective of any wireless communication systems, especially those offering broadband multimedia service. This paper describes Zero-Crossing IF-level(ZCIF) QPSK demodulator for high-speed wireless communications, and its hardware structures are discussed. ZCIF QPSK demodulator is mainly composed of symbol time circuit and carrier recovery circuit to estimate timing and phase-offsets. There are various schemes. Among them, we use Gardner algorithm and Decision-Directed carrier recovery algorithm which is most efficient scheme to warrant the fast acquisition and tracking to fabricate FPGA chip. The testing results of the implemented onto CPLD-FLEX10K chip show demodulation speed is reached up to 2.6［Mbps］. Actually in case of designing by ASIC, its speed may be faster than CPLD by 5 times. Therefore, it is possible to fabricate the ZCIF QPSK demodulator with speed of 10 Mbps.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2000.05a
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• pp.226-230
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• 2000

In this paper, we implemented the QPSK demodulator with a CPLD chip, and examined the results. DD(Decision Directed)-Gardner algorithm is used for STR loop and Decision-Directed algorithm is used for CPR loop. The speed of the QPSK demodulator implemented in FLEX10K chip can be guaranteed approximately 2[Mbpsl] transmission speed. In practical designed by ASIC, the speed is faster than that of CPLD by 5-6 times.

• Journal of the Institute of Electronics Engineers of Korea TC
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• v.45 no.2
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• pp.6-12
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• 2008

In uplink cable modem link operated in time-division multiple access mode, it is crucial to employ a suitable preamble pattern enabling frame detection, coarse timing/carrier recovery. Preamble pattern based on the constant envelope zero autocorrelation sequence is proposed for the uplink cable modem compliant to the data over cable service interface specification. Frame detection, coarse/fine timing and carrier recovery algorithms suitable for the proposed preamble pattern are also proposed. We check up the performances using numerical results.

• Journal of the Korean Society for Aeronautical & Space Sciences
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• v.44 no.3
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• pp.266-273
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• 2016

In this paper, we propose the signal processing techniques for the command link receiver mounted to aircrafts flying at a high speed. In order to acquire the various information transmitted from ground through radio frequency links, the wide received signal range must be guaranteed as well as the carrier synchronization and symbol synchronization be performed correctly within short pulse sections. After the synchronization step, we should be able to achieve theoretical performance of the modulation and demodulation scheme applied as deciding bit and symbol at the time appointed. By test results, we make sure that the proposed signal processing techniques can be effectively applied command link receiver mounted to aircrafts.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.34 no.10A
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• pp.807-813
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• 2009

A Satellite transponder is the Communication system to process signal with up-link signal recovery, and transmit to ground station through down-link. The orbit flight in the deep space causes high doppler shift in the received signals from the ground station so that the Carrier recovery and fast synchronization system are essential for the transponder system. The conventional analog transponder is employing the system's carrier recovery along with the PLL (Phase Locked Loop) designed for satellite's operation. This paper presents a digital carrier recovery scheme which can provide more reliable and software reconfigurable implementation technique for satellite transponder system without verifying scheme along with transponder designed for short distance or deep space satellite.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.37 no.3C
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• pp.251-258
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• 2012

In this paper, we propose a novel method of multi-node frequency synchronization for distributed networks. The proposed method synchronizes carrier frequencies of all nodes in the network and this enables new entry node to synchronize immediately. Moreover, when several groups exist in the network, inter-group synchronization method is proposed. The proposed distributed frequency synchronization method is expected to be very useful for the military operation scenario that new node entry is in a state of flux and group merging and splitting frequently happen.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.34 no.4C
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• pp.424-429
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• 2009

This paper suggests an autocorrelation function (AF) based carrier frequency offset (CFO) estimator based on a training sequence in flat fading channels. The proposed CFO estimator has the reduced computational burdens in the calculation of the AF when compared to AF-based conventional frequency estimators. The simulation results show that the proposed estimator achieves a better performance than the existing estimators. Furthermore, the performance of the proposed method has been observed to lie close to the Cramer-Rao lower bound (CRLB).