• Journal of the Institute of Electronics Engineers of Korea TC
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• v.46 no.11
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• pp.32-39
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• 2009

In this thesis, design effective elimination interference algorithm of ICS repeat system for repeater that improve frequency efficiency. Gennerally, LMS Algorithm apply to ICS repeat system. Error convergence speed and accuracy of LMS Algorithm are influenced by reference signal. For improve LMS Algorithm, suggest Adaptive searching channel estimate algorithm. For using channel characteristic, adaptive searching channel estimate algorithm make reference signal similar interference signal by convolution operation and complement LMS algorithm demerit. For make channel similar pratical channel, apply Jake's Rayleigh multi-path model. LMS algorithm and suggested adaptive searching channel estimate algorithm that have 16 taps apply to ICS repeat system under Rayleigh multi-path channel, so simulate with MATLAB. According to simulate, ICS repeat system with LMS algorithm show -40 dB mean square error convergent after 110 datas iteration and ICS repeat system with adaptive searching channel estimate algorithm show -80 dB mean square en-or convergent after 120 datas iteration. Analyze simulation result, suggested adaptive searching channel estimate algorithm show 40 dB accuracy than LMS algorithm.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.11 no.1
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• pp.46-55
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• 2007

The Newton-Raphson's algorithm for finding a floating point reciprocal and inverse square root calculates the result by performing a fixed number of multiplications. In this paper, an improved Newton-Raphson's algorithm is proposed, that performs multiplications a variable number. Since the number of multiplications performed by the proposed algorithm is dependent on the input values, the average number of multiplications per an operation is derived from many reciprocal and inverse square tables with varying sizes. The superiority of this algorithm is proved by comparing this average number with the fixed number of multiplications of the conventional algorithm. Since the proposed algorithm only performs the multiplications until the error gets smaller than a given value, it can be used to improve the performance of a reciprocal and inverse square root unit. Also, it can be used to construct optimized approximate tables. The results of this paper can be applied to many areas that utilize floating point numbers, such as digital signal processing, computer graphics, multimedia, scientific computing, etc.

• Convergence Security Journal
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• v.16 no.7
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• pp.113-120
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• 2016

This paper presents a new high-speed SHA-1 pipeline architecture having a computation delay close to the maximum critical path delay of the original SHA-1. The typical SHA-1 pipelines are based on either a hash operation or unfolded hash operations. Their throughputs are greatly enhanced by the parallel processing in the pipeline, but the maximum critical path delay will be increased in comparison with the unfolding of all hash operations in each round. The pipeline stage logics in the proposed SHA-1 has the latency is similar with the result of dividing the maximum threshold delay of a round by the number of iterations. Experimental results show that the proposed SHA-1 pipeline structure is 0.99 and 1.62 at the operating speed ratio according to circuit size, which is superior to the conventional structure. The proposed pipeline architecture is expected to be applicable to various cryptographic and signal processing circuits with iterative operations.

• Nuclear Medicine and Molecular Imaging
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• v.43 no.5
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• pp.459-467
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• 2009

Purpose: The maximum likelihood-expectation maximization (ML-EM) is the statistical reconstruction algorithm derived from probabilistic model of the emission and detection processes. Although the ML-EM has many advantages in accuracy and utility, the use of the ML-EM is limited due to the computational burden of iterating processing on a CPU (central processing unit). In this study, we developed a parallel computing technique on GPU (graphic processing unit) for ML-EM algorithm. Materials and Methods: Using Geforce 9800 GTX+ graphic card and CUDA (compute unified device architecture) the projection and backprojection in ML-EM algorithm were parallelized by NVIDIA's technology. The time delay on computations for projection, errors between measured and estimated data and backprojection in an iteration were measured. Total time included the latency in data transmission between RAM and GPU memory. Results: The total computation time of the CPU- and GPU-based ML-EM with 32 iterations were 3.83 and 0.26 see, respectively. In this case, the computing speed was improved about 15 times on GPU. When the number of iterations increased into 1024, the CPU- and GPU-based computing took totally 18 min and 8 see, respectively. The improvement was about 135 times and was caused by delay on CPU-based computing after certain iterations. On the other hand, the GPU-based computation provided very small variation on time delay per iteration due to use of shared memory. Conclusion: The GPU-based parallel computation for ML-EM improved significantly the computing speed and stability. The developed GPU-based ML-EM algorithm could be easily modified for some other imaging geometries.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.26 no.5B
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• pp.582-591
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• 2001

터보 부호는 반복적인 복호 알고리즘을 사용함으로써 가산성 백색 가우시안 잡음(AWGN) 채널 환경에서 Shannon 한계에 가까운 성능을 보이는 오류정정 방식으로 제안되었으나, 반복 연산량에 따른 복호 지연과 인터리버에 따른 지연에 의해 실시간 처리의 어려움이라는 문제점을 안고 있다. 본 논문에서는 터보 부호의 성능을 저하시키지 않는 범위에서 적절한 초기 임계값 설정에 따라 불필요한 반복 복호 횟수를 줄일 수 있는 터보 복호기 구조를 제안한다. 적절한 초기 임계값 설정은 LLR(Log-Likelihood Ratio)값의 평균값과 분산, 복호기의 출력에 대한 BER에 근거하여 여러 번의 모의 실험을 통해서 최적의 값으로 결정된다. 제안한 방식은 초기 임계값을 적절히 선택하면 손실이 없는 범위 내에서 반복횟수를 감소시킴으로써 기존의 정해진 반복횟수로 인한 큰 복호 지연을 미연에 방지하고, 이에 따른 계산량 감소는 저전력의 효과도 가져온다. 성능 평가를 위해 BER = $10^{-6}$이내이고, 전송속도가 32kbps 이상인 IMT2000의 고속 데이터 전송 환경에서 모의 실험을 하였다. 실험 결과로 기존의 정해진 반복횟수를 갖는 터보 복호기에 비해 SNR 변동(0~3dB)에서 평균적으로 55~90% 정도의 감소된 반복횟수를 검증하였다.

• Proceedings of the Korea Information Processing Society Conference
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• 2002.11b
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• pp.901-904
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• 2002

정보의 암호화와 인증, 디지털 서명등에 효율적인 공개키 암호 시스템의 주 연산은 모듈라 멱승 연산이며 이는 모듈라 곱셈의 연속적인 반복 수행으로 표현될 수 있다. 본 논문에서는 Montgomery 모듈라 곱셈 알고리즘을 사용하여 모듈라 곱셈을 효율적으로 수행하기 위한 모듈라 멱승 연산기를 구현하였으며 Montgomery 모듈라 곱셈시 발생하는 케리 진파 문제를 해결하기 위하여 CPA을 대신하는 CSA를 사용함으로써 멱승 연산시 발생하는 지연시간을 최소화시키는 결과가 얻어짐을 보였다. 본 논문에서는 Montgomery 모듈라 멱승 연산기 구현을 위하여 VHDL 구조적 모델링을 통하여 Synopsys사의 VSS와 Design analyzer를 이용한 논리 합성을 하였고 Mentor Graphics사 Model sim 및 Xilinx사 Design manager의 FPGA 시뮬레이션을 수행하여 성능을 검증 하였다.

• Proceedings of the Korean Society for Emotion and Sensibility Conference
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• 1999.11a
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• pp.139-144
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• 1999

본 논문에서는 45명의 남자 대학생들에게 연산을 수행하게 한 후, 연산스트레스를 측정하기 위한 생리 파라메터의 추출에 대하여 연구하였다. 파라메터를 추출하기 위해서 1) 정규분포화를 위한 변환 2) 상관관계를 통해 상호관련성이 높은 파라메터를 조사 3) 휴식기간과 연산작업간의 파라메터의 값 비교를 통한 파라메터 표준화 4) 각 파라메터에 대해서 반복측정자료의 분산분석법을 통하여 검정함으로써 통계적으로 유의적인 차이가 있는 파라메터를 선정하였다. 위와 같은 절차를 통하여 연산스트레스의 지수화에 필요한 생리 파라메터로 Heart Rate, HRV의 LF/HF, HRV의 MF/(LF+HF), Return Map의 분산, Mean Temperature, GSR-Mean과 호흡수가 최종적으로 선정되었다.

• Journal of the Korea Institute of Information Security & Cryptology
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• v.19 no.6
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• pp.63-70
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• 2009

Many research results show that RSA system mounted using conventional binary exponentiation algorithm is vulnerable to some physical attacks. Recently, Schmidt and Hurbst demonstrated experimentally that an attacker can exploit secret key using faulty signatures which are obtained by skipping the squaring operations. Based on similar assumption of Schmidt and Hurbst's fault attack, we proposed new fault analysis attacks which can be made by skipping the multiplication operations or computations in looping control statement. Furthermore, we applied our attack to Montgomery ladder exponentiation algorithm which was proposed to defeat simple power attack. As a result, our fault attack can extract secret key used in Montgomery ladder exponentiation.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.38C no.3
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• pp.311-317
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• 2013

In this paper, we proposed high speed LDPC decoding algorithm based on DVB-S2 standard for applying marine communications in order to multimedia transmission. For implementing the high speed LDPC decoder, HSS algorithm which reduce the iteration numbers without performance degradation is applied. In HSS algorithm, check node update units are update at the same time of bit node update. HSS can be accelerated to the decoding speed because it does not need to separate calculation of the bit nodes, However, check node calculation blocks need many clocks because of just one memory is used. Therefore, this paper proposed partial memory structure in order to reduced the delay and high speed decoder is possible. The results of the simulation, when the max number of iteration set to 30 times, decoding throughput of HSS algorithm is 326 Mbit/s and decoding speed of proposed algorithm is 2.29 Gbit/s. So, decoding speed of proposed algorithm more than 7 times could be obtained compared to the HSS algorithm.

• Journal of IKEEE
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• v.20 no.3
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• pp.209-219
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• 2016

SVM is a machine learning method used for image processing. It is well known for its high classification performance. We have to perform multiple MAC operations in order to use SVM for image classification. However, if the resolution of the target image or the number of classification cases increases, the execution time of SVM also increases, which makes it difficult to be performed in real-time applications. In this paper, we propose an hardware architecture which enables real-time applications using SVM classification. We used parallel architecture to simultaneously calculate MAC operations, and also designed the system for several feature extractors for compatibility. RBF kernel was used for hardware implemenation, and the exponent calculation formular included in the kernel was modified to enable fixed point modelling. Experimental results for the system, when implemented in Xilinx ZC-706 evaluation board, show that it can process 60.46 fps for $1360{\times}800$ resolution at 100MHz clock frequency.