• Journal of the Korea Society of Computer and Information
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• v.25 no.6
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• pp.99-107
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• 2020

In this paper, we analyze the characteristics of mobile cache, which is used to improve the data access speed when executing applications on mobile devices, and verify the importance of mobile cache through a cache data access experiment. The mobile device market has grown at a fast pace over the past decade; however, battery limitations and size, price considerations restrict the usage of fast hardware. Thus, their performance are supplemented by using a memory buffer structure such as the cache memory. The analysis mainly focuses on cache size, hierarchical structure of cache, cache replacement policy, and the effect these features has on mobile performance. For the experimental data, we applied a data set from a microprocessor system study, originally used to test the cache performance. In the experimental results, the average data access speed on a mobile device showed a performance improvement of up to 10 times with the presence of cache memory than without. Accordingly, the cache memory was helpful for the performance improvement of a mobile device when the specifications were identical.

• Proceedings of the Korea Information Processing Society Conference
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• 2013.05a
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• pp.93-96
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• 2013

모바일 환경에서 전력 손실이 중요한 문제 중 하나가 됨에 따라, MRAM과 플래시메모리와 같은 비 휘발성 메모리가 차세대 모바일 컴퓨터에 널리 사용될 것이다. 본 논문에서는 DRAM/MRAM 하이브리드 메인 메모리의 제한적인 쓰기 연산 성능을 고려한 효율적인 버퍼 캐시 기법을 연구했다. 제안한 기법은 MRAM 의 제한적인 쓰기 연산 성능을 고려하고 플래시 메모리 저장 장치의 삭제 연산 횟수를 최소화한다.

• The Journal of the Institute of Internet, Broadcasting and Communication
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• v.21 no.2
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• pp.27-32
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• 2021

This paper proposes an energy-efficient cache and memory management scheme for next-generation IoT devices. The proposed scheme adopts a low-power phase-change memory (PCM) as the main memory of IoT devices, aims at minimizing the write traffic to PCM, which is vulnerable to write operations. Specifically, when a cache block of the last-level cache memory is flushed to main memory, the cache block that causes less writes to PCM is preferentially replaced by tracking the modifications of each cache line that constitutes the cache block. In addition, by considering the reference bit of the cache block and the dirty bit of the cache lines, our scheme reduces the energy consumption without degrading the memory system performances. Through simulations using SPEC benchmarks, it is shown that the proposed scheme reduces the write traffic to PCM by 34.6% on average and the power consumption by 28.9%, without memory performance degradations.

• Journal of KIISE
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• v.42 no.11
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• pp.1314-1321
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• 2015

Mobile devices employ buffer cache mechanisms, just as in computer systems such as desktops or servers, to mitigate the performance gap between main memory and secondary storage. However, DRAM has a problem in that it accelerates battery consumption by performing refresh operations periodically to maintain the stored data. In this paper, we propose a novel buffer cache scheme to increase the battery lifecycle in mobile devices based on a hybrid main memory architecture consisting of DRAM and non-volatile PCM. We also suggest a new buffer cache policy that allocates buffers based on process states to optimize the performance and endurance of PCM. In particular, our algorithm allocates each page to the appropriate position corresponding to the state of the application that owns the page, and tries to ensure a rapid response of foreground applications even with a small amount of DRAM memory. The experimental results indicate that the proposed scheme reduces the elapsed time of foreground applications by 58% on average and power consumption by 23% on average without negatively impacting the performance of background applications.

• Journal of KIISE:Computer Systems and Theory
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• v.37 no.5
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• pp.285-291
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• 2010

Flash memory has many good features such as small size, shock-resistance, and low power consumption, but the cost of flash memory is still high to substitute for hard disk entirely. Recently, some mobile devices, such as laptops, attempt to use both flash memory and hard disk together for taking advantages of merits of them. However, existing OSs (Operating Systems) are not optimized to use the heterogeneous storage media. This paper presents a new buffer cache management scheme. First, we allocate buffer cache space according to access patterns of block references and the characteristics of storage media. Second, we prefetch data blocks selectively according to the location of them and access patterns of them. Third, we moves destaged data from buffer cache to hard disk or flash memory considering the access patterns of block references. Trace-driven simulation shows that the proposed schemes enhance the buffer cache hit ratio by up to 29.9% and reduce the total I/O elapsed time by up to 49.5%.

• Proceedings of the Korea Information Processing Society Conference
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• 2013.11a
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• pp.44-45
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• 2013

전 세계의 스마트폰 보급률이 증가와 함께 새로운 형태의 스마트 워치, 구글 글래스 등의 모바일 장비들이 등장하고 있다. 이는 제한된 자원을 사용하는 스마트폰 환경에서 효율적으로 CPU, 메모리, 저장 장치들을 효과적으로 사용하기 위한 연구를 필요로 한다. 이에 본 논문에서는 안드로이드 환경에서 부족 메모리의 공간 확보를 위해 동일한 내용의 페이지 캐시를 찾고, 중복 제거하는 기법을 제안한다. 이는 부족한 메모리 공간 확보와 캐시를 지속하여 I/O 연산의 빈도를 줄여 스마트폰 성능 향상을 가져올 것으로 기대된다.

• The KIPS Transactions:PartA
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• v.14A no.1 s.105
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• pp.55-62
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• 2007

Uptime of embedded processors for mobile devices are dependent on battery consumption. Especially the large portion of power consumption is known to be due to cache management in embedded processors. This paper proposes an energy efficient data cache structure for high performance embedded processors. High performance prefetching data cache issues prefetching instructions before issuing demand-fetch instructions based on reference predictions. These prefetching instruction bring reduction on memory delay by improving cache hit ratio, but on the other hand those increase energy consumption in proportion to the number of prefetching instructions. In this paper, we adopt tag history table on prefetching data cache for reducing energy consumption by minimizing parallel tag comparison. Experimental results show the proposed data cache improves performance on energy consumption as well as memory delay.

• Journal of the Korea Society of Computer and Information
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• v.14 no.4
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• pp.9-17
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• 2009

In this paper, we propose a dynamic load distribution technique at the operating system level in mobile storage systems with a heterogeneous storage pair of a small form-factor and disk and a flash memory, which aims at saving energy consumption as well as enhancing I/O performance. Our proposed technique takes a combinatory approach of file placement and buffer cache management techniques to find how the load can be distributed in an energy and performance-aware way for a heterogeneous mobile storage air of a hard disk and a flash memory. We demonstrate that the proposed technique provides better experimental results with heterogeneous mobile storage devices compared with the existing techniques through extensive simulations.

• Journal of the Korea Society of Computer and Information
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• v.14 no.2
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• pp.45-57
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• 2009

ETexture mapping is a technique used for adding reality to an image in 3D graphics. However. this technique becomes the bottleneck of the 3D graphics pipeline because it requires large processing power and high memory bandwidth. For reducing memory latency in texture mapping, texture cache is used. As portable devices become smaller and they have power constraint, it is important to reduce the area and the power consumption of the texture cache. In this paper we propose using a small texture cache to reduce the area and the power consumption of the texture cache. Furthermore, we propose techniques to keep a performance comparable to large texture caches by using prefetch techniques and a victim cache. Simulation results show the proposed small texture cache can reduce the area and the power consumption up to 70% and 60%, respectively, by using $1{\sim}2K$ bytes texture cache compared to the conventional 16K bytes cache while keeping the performance.

• Review of KIISC
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• v.33 no.5
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• pp.25-38
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• 2023

중요 데이터와 서비스를 격리하여 보호하기 위한 신뢰연산기술이 모바일 기기에서 널리 활용되고 있다. 신뢰연산기술은 보통 하드웨어 기반 접근제어를 통해 메모리, 레지스터, 캐시 등의 하드웨어 자원을 공격자로부터 격리하는 신뢰실행영역을 시스템 내에 생성할 수 있게 한다. 하지만 보호 대상 소프트웨어에 악용 가능한 취약점이 존재할 경우 그 보안성이 파훼될 수 있다. 따라서 신뢰실행영역 내에도 소프트웨어에 대한 공격 효율성을 최소화할 수 있는 보안 기술이 적용되어야 한다. 모바일 디바이스에 주로 적용된 ARM 아키텍처에서도 포인터 인증, 메모리 태깅과 같은 다양한 하드웨어 기반 보안기술들이 정의되고 있으며 최신 고사양 모바일 디바이스를 중심으로 적용되고 있다. 하지만 아키텍처 버전에 따라 가용한 하드웨어 보안 기술이 상이하기 때문에 보안기술의 범용성을 향상시키기 위한 방안 또한 중요하게 연구되어야 한다. 본고에서는 모바일 신뢰연산기술의 보안성을 향상시키기 위한 대표적인 범용 보안 기술들에 대해 소개한다. 특히 유저서비스, 운영체제, 하이퍼바이저의 보안성을 향상시키기 위해 제안된 디버깅 와치포인트 기반 보안 기술들에 대해 분석하고 그 한계와 타 아키텍처 확장 가능성에 대해서 논의한다.