• Proceedings of the Korean Information Science Society Conference
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• 2000.04a
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• pp.133-135
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• 2000

분산 공유 메모리 상에서 클라이언트들은 네트워크를 통해 원격 공유 메모리 상으로 접근하게 된다. 접근 시에 클라이언트들은 접근 정보를 자신의 지역 캐쉬에 저장해 두었다가 필요시에 인출해서 사용한다. 그러나 시간이 경과함에 따라 다른 클라이언트들에 의해서 데이터 갱신이 이루어질 수 있다. 이에 본 논문에서는 원격 데이터 정보를 객체로 설정하여 이 객체를 관리하여 분산 공유 메모리 상에서 데이터 일관성을 유지하고자 한다. 객체 중복을 통해서 분산 객체 시스템을 구성하였을 때 기존의 중복 기법에서 사용하는 일관성 비용 이외에 별도의 추가 비용이 없이도 제한적으로 병렬 수행의 효과를 볼 수 있다. 또한 중복 기법에 있어서 가장 큰 오버헤드로 알려진 일관성 유지비용을 최소화시키기 위하여 이 비용을 결정하는 가장 핵심저인 요소인 객체의 복사본의 수를 동시적으로 변화시키면서 관리함으로써 전체 수행 시간의 측면에서 많은 향상을 가져왔다.

• Proceedings of the Korea Information Processing Society Conference
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• 2012.11a
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• pp.195-196
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• 2012

하드웨어 플랫폼은 다수 코어 아키텍처의 메모리 대역폭을 만족시키기 위해 NUMA 구조로 설계되고 있다. 이러한 NUMA 구조에서 다른 노드의 메모리에 접근할 경우, 해당 노드의 메모리 접근에 비해 1.5~2배 지연이 발생한다. 따라서 이러한 특성을 고려하는 NUMA 시스템 기반 스케줄러가 필요하다. 본 논문에서는 NUMA 기반 스케줄러 설계를 위해 고려되어야 할 사항에 대해 분석해 본다. 분석 결과, 공유 자원 경쟁과 리모트 접근을 최소화하는 것이 NUMA 스케줄러 설계의 핵심이라는 것을 확인할 수 있었다. 뿐만 아니라 같은 노드에서 실행되는 워크로드의 조합 및 캐시 오염 태스크 관리, 그리고 노드별 남아있는 메모리 정보 또한 고려되어야 한다는 것을 확인할 수 있었다.

• The KIPS Transactions:PartD
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• v.14D no.6
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• pp.675-688
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• 2007

Memory access errors are frequently occurred in C programs. A number of tools and research works have been trying to detect the errors automatically. However, they have one or more of the following problems: inability to detect all memory errors, changing the memory allocation mechanism, incompatibility with libraries, and excessive performance overhead. In this paper, we suggest a new method to solve these problems, and then present a result of comparison to the previous research works through the experiments. Our approach consists of two phases. First is to transform source code at compile time through inserting instrumentation into the source code. And second is to detect memory errors at run time with a bitmap that maintains information about memory allocation. Our approach has improved the error detection abilities against the binary code analysis based ones by using the source code analysis technique, and enhanced performance in terms of both space and time, too. In addition, our approach has no problem with respect to compatibility with shared libraries as well as does not need to modify memory allocation mechanism.

• Journal of KIISE:Computer Systems and Theory
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• v.32 no.11_12
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• pp.541-556
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• 2005

The memory access latency of the system has been a primary factor of performance degradation in single-processor system and multi-processor system. The remote memory access latency takes a lot of overhead over the local memory access latency especially in the distributed shared-memory system. To resolve this problem, the multi-level cache architecture that contains a remote cache in the multi-processor system has been proposed. In this paper, we propose a new cache replacement policy that improves the performance of the multi-processor system with the remote cache. If the multi-level cache keeps the multi-level inclusion(MLI) property and uses the LRU(Least Recently Used) cache replacement policy, the LRU information of the higher-level cache(a processor cache) would be different with that of the lower-level cache(a remote cache). In this situation, the replacement of a remote cache line can induce the exchange of a processor cache line that is used by the processor. It is a main factor of performance degradation in a whole system. To alleviate this disadvantage of the LRU replacement polity, the new policy analyses tht processor's remote memory access pattern of each node and uses this information to reduce the number of invalidations of the useful cache line in the higher-level cache. The new replacement policy of the remote cache can improve the performance by $3.5\%$ in maximum and $2.5\%$ in average on SPLASH-2 benchmarks, compared to the general LRU cache replacement policy.

• Proceedings of the Korea Information Processing Society Conference
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• 2014.04a
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• pp.15-17
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• 2014

멀티미디어를 비롯한 많은 스트리밍 어플리케이션은 에너지 소비의 상당한 부분을 데이터 접근 연산 실행 명령어에 의해서 소비된다. 이러한 어플리케이션에서는 데이터 재사용성을 이용하여 에너지 소모량을 절감할 수 있다. 빈번히 사용되는 데이터를 고속의 상위 계층 메모리에 상주시켜 메인메모리 접근 횟수를 줄인다. 결과적으로 메모리 서브시스템에서 에너지 소모를 절감할 수 있게 된다. 본 연구에서는 어플리케이션의 재사용성을 분석하여 해당 어플리케이션에 특화된 스크래치패드 메모리 서브시스템 구성을 탐색하는 기법을 제안하고자 한다. 제안된 기법을 사용하면 하드웨어 제어 캐시 메모리와 비교하여 약 49% 에너지 소모를 절감하는 것이 가능하다.

• KIPS Transactions on Computer and Communication Systems
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• v.2 no.2
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• pp.59-66
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• 2013

In this paper, we proposed an optimal ILP algorithm on memory address code generation for DSP in embedded system. This paper using 0-1 ILP formulations DSP address generation units should minimize the memory variable data layout. We identify the possibility of the memory assignment of variable based on the constraints condition, and register the address code which a variable instructs in the program pointer. If the process sequence of the program is declared to the program pointer, then we apply the auto-in/decrement mode about the address code of the relevant variable. And we minimize the loads on the address registers to optimize the data layout of the variable. In this paper, in order to prove the effectiveness of the proposed algorithm, FICO Xpress-MP Modeling Tools were applied to the benchmark. The result that we apply a benchmark, an optimal memory layout of the proposed algorithm then the general declarative order memory on the address/modify register to reduce the number of loads, and reduced access to the address code. Therefor, we proved to reduce the execution time of programs.

• The Transactions of the Korea Information Processing Society
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• v.3 no.1
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• pp.118-126
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• 1996

Memory hierarchy is a useful mechanism for improving the memory access speed and making the program space larger by layering the memories and separating program spaces from memory spaces. However, it needs at least two memory accesses for each data reference : a TLB(Translation Lookaside Buffer) access for the address translation and a data cache access for the desired data. If the cache size increases to the multiplication of page size and the cache associativity, it is difficult to access the TLB with the cache in parallel, thereby making longer the critical timing path in the processor. To achieve such parallel accesses, we present the hybrid mapped TLB which combines a direct mapped TLB with a very small fully-associative mapped TLB. The former can reduce the TLB access time. while the latter removes the conflict misses from the former. The trace-driven simulation shows that under given workloads the proposed TLB is effective even when a fully-associative mapped TLB with only four entries is added because the effects of its increased misses are offset by its speed benefits.

• Proceedings of the Korean Information Science Society Conference
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• 2002.10c
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• pp.376-378
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• 2002

가상 메모리 관리에서 가장 근 문제점은 느린 보조기억 장치의 속도와 빠른 주기억장치의 속도 차이에서 나타나는 성능 저하라고 할 수 있다 요구 페이징 기법에서 Page Fault가 일어나면 페이지 교체 정책에 의해 필요 없는 page들을 swap device로 이동을 시킨다. 이때 느린 보조기억장치의 접근 속도로 인한 응답시간의 지연은 전체적인 시스템 성능의 저하를 초래한다. 그래서 Swap Device로의 접근 횟수와 페이지의 크기를 줄일 수 있다면 Page Out되는 응답시간을 높일 수 있을 것이다. 따라서 본 논문에서는 가상 메모리 압축 시스템을 설계하여 Swap Out 되는 시간을 줄여 시스템의 전체적인 성능 향상을 위한 시스템을 구현한다.

• Journal of KIISE:Computer Systems and Theory
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• v.34 no.9
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• pp.445-458
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• 2007

This article presents a novel infrastructure for large-memory database processing using commodity hardware with operating system support. We exploit inexpensive PCs and a high-speed network capable of Remote Direct Memory Access (RDMA) operations to build a new memory hierarchy between fast volatile memory and slow disk storage. The new memory hierarchy guarantees a reasonable response time, and its storage size enables us to run large-memory database systems with little performance degradation. The proposed architecture has two main components: (1) a remote memory system inside the Linux kernel to manage other computers' memory pages efficiently and (2) a remote memory pager responsible for manipulating remote read/write operations on remote memory pages. We insist that the proposed architecture is practical enough to support the rigorous demands of commercial in-memory database systems by demonstrating the performance of publicly available main-memory databases (e.g., MySQL) on our prototyped system. The experimental results show very interesting results from the TPC-C benchmark.

• Journal of KIISE
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• v.43 no.5
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• pp.524-530
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• 2016

The desire to access data faster and the growth of next-generation memories such as non-volatile memories, contribute to the development of research on memory file systems. It is recommended that memory mapped file I/O, which has less overhead than read-write I/O, is utilized in a high-performance memory file system. Memory mapped file I/O, however, brings a page table overhead, which becomes one of the big overheads that needs to be resolved in the entire file I/O performance. We find that same overheads occur unnecessarily, because a page table of a file is removed whenever a file is opened after being closed. To remove the duplicated overhead, we propose the mapping cache, a technique that does not delete a page table of a file but saves the page table to be reused when the mapping of the file is released. We demonstrate that mapping cache improves the performance of traditional file I/O by 2.8x and web server performance by 12%.