• Journal of the Korean Society for Aeronautical & Space Sciences
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• v.49 no.11
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• pp.893-900
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• 2021

In this study, air density in a narrow test section is measured using a laser absorption spectroscopy system that detects oxygen absorption lines. An absorption line pair at 13156.28 and 13156.62 cm^-1 are detected. A gas chamber with a height of 40 mm is used as a narrow test section. A triangular spiral-shaped laser path is applied in the gas chamber to amplify absorption strength by extending laser beam path length. A well-known logarithm amplifier and a secondary amplifier are used to electrically amplify absorption signal. An AC-coupling is applied after the logarithm amplifier for signal saturation prevention and noise suppression. Procedure of calculating spectral absorbance from output signal is introduced considering the logarithm amplifier circuit configuration. Air density is determined by fitting the theoretically calculated spectral absorbance to the measured spectral absorbance. Test conditions with room temperature and a pressure range of 10~100 kPa are made in a gas chamber using a Bourdon pressure gauge. It is confirmed that air density in a narrow test section can be measured within a 16 % error through absorption signal amplification using a triangular spiral-shaped beam path and a logarithm amplifier.

• Journal of the KSME
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• v.25 no.2
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• pp.130-136
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• 1985

확정적 계측신호에 극한시키며 현장 혹은 연구실에 종사하고 있는 기계기술자에게 필요로 하는 애널로그계측과 디지틀계측의 특성과 계측시스템의 구성, 연산증폭기(Op. Amp)의 원리 및 응용, 측정신호의 선형화, 마이크로 프로세서의 원리 A/D, D/A 변환기의 원리 및 응용, 자료처리시 스템, 센서의 원리 및 응용, 디지틀계측시스템의 최근동향등 메카트로닉스시대에서 요청되는 계 측공학의 주요과제에 대하여 기술한다.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.22 no.6
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• pp.641-647
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• 2011

This paper describes a design and fabrication of SDLVA. The SDLVA operates 0.5~2.0 GHz with -70~0 dBm dynamic range. The SDLVA is consisted of 5-stage RF block, 2-stage detector block and summation circuit using clamping op-amp to improve video linearity. The result of measure, SDLVA of RF path has over 73 dB small-signal gain and 10.1~12.2 dBm saturation power. The video path has 25 mV/ dB${\pm}$1.0 mV and under ${\pm}$1.5 dB video linearity.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.13 no.6
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• pp.507-513
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• 2002

In this paper, the receiver using Heterodyne type is designed and implemented for a pulse radar at 9.4 GHz. The If amplifier, which occupies a significant size in a Heterodyne receiver for pulse radars, can be removed. Furthermore, by using detector logarithmic video amplifier in baseband, the receiver has a small size and it's characteristic shows a high dynamic range and sensitivity. From the results of measurements, the minimum receiver power of -70 dBm and selectivity of 55 dB are obtained.

• Journal of the Korea Convergence Society
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• v.7 no.3
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• pp.77-85
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• 2016

We propose a digital signal processing technic that can compensate the non-linearity inherent in audio amplifiers, and present the result of the simulation. The inherent non-linearity of the audio power amplifier arising from analog devices is compensated via a digital signal processing technic consisting of indirect learning architecture and an adaptive filter. The simulation results show that the compensator can be realized using a third-order polynomial and compensates odd-order non-linearity efficiently. The even-oder non-linearity is mainly due to the dc offset at the output, which is difficult to eliminate with the proposed method. Care must be taken in designing the bias circuit to avoid the DC offset at the output. The proposed technic has significance in that digital signal processing technic can compensate for the impairment that is an inherent characteristic of an analog system.

• The Magazine of the IEIE
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• v.7 no.2
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• pp.13-26
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• 1980

지난 20년 동안 디지털(digital) 통신은 괄목할 만한 발전을 해 왔다. 이는 컴퓨터, 집적회로, 디지털 신호처리 기술의 급격한 발전으로부터 직접적으로 크게 영향을 받았기 때문이다. 디지털 통신은 잡음, 타신호와의 간섭, 비선형 증폭기 사용에 의한 성능 저하 등의 어네로그(analog) 통신에서의 문제점들을 해결하고, 또한 대형집적회로 또는 마이크로프로세서를 사용함으로써의 이점, 즉 time sharing, 기기 유지관리의 용이성, 경제적인 점 등 여러 가지 장점이 있기 때문에 앞으로 그 발전은 가속화되어 결국 어네로그 통신과 대체될 전망이다. 여기에서는 현재 디지털 통신의 주종이 되고 있는 PCM을 중심으로 한 통신시스템(PCM 부호화, 교환, 다종화, 회로구성)을 설명하고 비교적 새로운 분야인 컴퓨터통신, 인공위성통신, 광통신, 디지털 통신에서의 대역폭 축소와 channel capacity를 증가시키는 방법들을 토의함으로써 디지털 통신기술의 현황과 앞으로의 전망에 관하여 검토하였다.

• Journal of IKEEE
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• v.19 no.1
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• pp.87-93
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• 2015

In this paper, a $145{\mu}W$, 87dB SNR, Low power 3rd order Sigma-Delta Modulator with Op-amp sharing is proposed. Conventional architecture with analog path and digital path is improved by adding a delayed feed -forward path for disadvantages that coefficient value of the first integrator is small. Proposed architecture has a larger coefficient value of the first integrator to remove the digital path. Power consumption of proposed architecture using op-amp sharing is lower than conventional architecture. Simulation results for the proposed SDM designed in $0.18{\mu}m$ CMOS technology with power supply voltage 1.8V, signal bandwidth 20KHz and sampling frequency 2.8224MHz shows SNR(Signal to Noise Ratio) of 87dB, the power consumption of $145{\mu}W$.

• Journal of the Korean Institute of Telematics and Electronics
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• v.7 no.2
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• pp.21-25
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• 1970

A Possibility of improving the temperature behavior by the use of a balanced diode compensation circuit in a Digital to Analogue converter is studied. Better linearity is achieved by eliminating the ladder network for the summation by means of an operational amplifier. Speed Consideration are taken to achieve 1.5 mesa bits per second with more than 80% useful plateau.

• Journal of Biomedical Engineering Research
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• v.7 no.1
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• pp.59-66
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• 1986

A prototype ultrasound sector B-scanner has been developed where the front-end hardware refers to all the necessary circuits for transmitting the ultrasound pulses into the human body and receiving the reflected echo signals from it. The front-end hardware can generally be divided into three parts, i.e., a pulse generator for insonification, a receiver which is responsible for processing of low-level analog signals, and a steering controller for driving the mechanical sector probe whose functions and design concepts are described in this paper. The front-end hardware is implemented which incorporates the following features: improvement of the axial resolution using a circuit which reduces the ring-down time, flexibility of generating time-gain compensation curve, and adoption of a one-chip microcomputer for generating the rate pulses based on the sensor output waveforms.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.39 no.7
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• pp.97-103
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• 2002

In this paper, a Logarithmic Video Amplifier(LVA) for radar system or satellite communications is described. The proposed LVA is composed of a input stage, amplification stage, and output stage. As well as a novel series-parallel architecture is proposed for the purpose of wide dynamic range and high speed operation, a newly developed input stage is designed in order to control the voltage level between LVA and detector diode. The LVA is fabricated with a 1.5um 2-poly 2-metal n-well Bi-CMOS technology, and the chip area is 1310 um x 1540 um. From the experimental results, it consumes 190 mW at 10V power supply, the chip has 60 dB dynamic range and 100ns falling time.