• Journal of the Korea Institute of Information and Communication Engineering
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• v.26 no.10
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• pp.1537-1544
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• 2022

When designing chip, it considers design specification, timing problem, and clock synchronization on place & route (P&R) process. P&R process is complicated because of considering various factors. Chip uses clock tree synthesis (CTS) to reduce clock path delay. The purpose of this study is to examine shallow-CTS algorithm for checking clock tree synthesizable. Using open source Parser-Verilog, register transfer level (RTL) synthesizable Verilog file is parsed and it uses Pre-CTS and Post-CTS process that is included shallow-CTS. Based on longest clock path in the Pre-CTS and Post-CTS stages, the standard deviation before and after buffer insertion is compared and analyzed for the accuracy of CTS. In this paper, It is expected that the cost and time problem could be reduced by providing a pre-clock tree synthesis verification method at the RTL level without confirming the CTS result using the time-consuming licensed EDA tool.

• The KIPS Transactions:PartA
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• v.18A no.6
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• pp.249-254
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• 2011

This paper describes an efficient design of the interpolation circuit to generate the luma and chroma sub-pixels for H.264 motion estimation. The circuit based on the proposed architecture does not require any input data buffering and processes the horizontal, vertical and diagonal sub-pixel interpolations in parallel. The performance of the circuit is further improved by simultaneously processing the 1/2-pixel and 1/4-pixel interpolations for luma components and the 1/8-pixel interpolations for chroma components. In order to reduce the circuit size, we store the intermediate data required to process all the interpolations in parallel in the internal SRAM's instead of registers. We described the proposed circuit at register transfer level and verified its operation on FPGA board. We also synthesized the gate-level circuit using 130nm CMOS standard cell library. It consists of 20,674 gates and has the maximum operating frequency of 244MHz. The total number of SPSRAM bits used in our circuit is 3,232. The size of our circuit (including logic gates and SRAM's) is smaller than others and the performance is still comparable to them.

• Journal of the Korea Society of Computer and Information
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• v.15 no.1
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• pp.13-21
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• 2010

IEEE 1149.1 test architecture was proposed to support the test of elements within the boards. It is a large serial shift register that uses the TDI pin as an input and the TDO pin as an output. Even though it performs the board level test perfectly, there is a problems of running system level test when the boards are equipped to the system. To test real time operation signal on test pin, output speed of serial shift register chain must be above double clock speed of shift register. In this paper, we designed a runtime test architecture and a runtime test procedure under running system environments to capture runtime signal at system clock rate. The suggested runtime test architecture are simulated by Altera Max+Plus 10.0. through the runtime test procedure. The simulation results show that operations of the suggested runtime test architecture are very accurate.

• The Journal of the Institute of Internet, Broadcasting and Communication
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• v.20 no.3
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• pp.181-187
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• 2020

In this paper, we proposed a register allocation algorithm and resource allocation algorithm in the high level synthesis process for the SoC design synthesis system of high performance vehicles We have analyzed to the operator characteristics and structure of datapath in the most important high-level synthesis. We also introduced the concept of virtual operator for the scheduling of multi-cycle operations. Thus, we demonstrated the complexity to implement a multi-cycle operation of the operator, regardless of the type of operation that can be applied for commonly use in the resources allocation algorithm. The algorithm assigns the functional operators so that the number of connecting signal lines which are repeatedly used between the operators would be minimum. This algorithm provides regional graphs with priority depending on connected structure when the registers are allocated. The registers with connecting structure are allocated to the maximum cluster which is generated by the minimum cluster partition algorithm. Also, it minimize the connecting structure by removing the duplicate inputs for the multiplexor in connecting structure and arranging the inputs for the multiplexor which is connected to the operators. In order to evaluate the scheduling performance of the described algorithm, we demonstrate the utility of the proposed algorithm by executing scheduling on the fifth digital wave filter, a standard bench mark model.

• Proceedings of the Korea Institute of Convergence Signal Processing
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• 2005.11a
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• pp.339-342
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• 2005

동적 부분 재구성은 FPGA 칩에 구현된 디자인에서 변경이 필요한 부분만 재구성하여 줌으로써 실시간적 재구성을 가능하게하는 방법이다. 동적 부분 재구성에 대한 많은 연구를 통하여 게이트 수준의 부분 재구성이 가능하지만, 설계 복잡도가 큰 시스템을 설계시에 게이트 수준의 부분 재구성 방법은 부적적하다. 본 논문에서는 Xilinx에서 제고하는 버스 매크로를 사용하여 모듈 기반의 부분 재구성 기법에 대하여 기술하며, 곱셈기, 레지스터, 그리고 ripple carry adder로 구성된 회로에서 ripple carry adder를 carry lookahead adder로 재구성한다.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.38 no.3
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• pp.220-228
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• 2001

Simulation of an instruction set is essential to design and optimize new microprocessors, and to develop application programs. Though many simulation tools are widely used, their low-level description and simulation make users construct simulators difficult and spend a lot of time for simulation. We developed an automatic generator of instruction set simulators that perform register-transfer-level simulation. This automatic generator might be adaptable so as to be suitable for new modification or different conditions in designing microprocessors. In this paper, we describe a structure of automatic generation system and an implementation details.

• Proceedings of the Korean Institute of Intelligent Systems Conference
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• 1997.11a
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• pp.87-92
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• 1997

본 논문은 저비용이면서 정확한 제어를 수행하는 새로운 퍼지 제어기의 VHDL 설계 및 시뮬레이션을 다룬다. 제안한 퍼지 제어기 (Fuzzy Logic Controller : FLC)의 정확한 비퍼지화 연산시 소속값뿐 아니라 소속 함수의 폭을 고려함으로서 ？어진다. 제안한 퍼지 제어기 저비용성은 기존의 FLC를 다음과 같이 개조함으로서 이루어진다. 먼저, MAX-MIN 추론이 레지스터 파일의 형태로 쉽게 구현 가능한 read-modify-write 연산에 의해 대치된다. 두 번째, COG 비퍼지화기에서 요구하는 제산 연산을 모멘트 균형점의 탐색에 의해 피할 수 있다. 제안한 COG 퍼지화기는 곱셈기가 부가적으로 요구되며 모멘트 균형점의 탐색 시간이 오래 걸리는 단점이 있다. 부가적 곱셈기 요구에 의한 하드웨어 복잡도 증가 문제는 곱셈기를 확률론적 AND 연산에 의해 해결할 수 있고, 오랜 탐색 시간 문제는 coarse-to fine 탐색 알고리즘에 의해 크게 경감될 수 있다. 제안한 퍼지 제어기의 각 모듈은 VHDL에 의해 구조적 수준 및 행위적 수준에서 기술되고, 이들이 제대로 동작하는지 여부를 SYNOPSYS사의 VHDL 시뮬레이션 상에서 트럭 후진 주차 문제에 적용하여 검증하였다.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.45 no.12
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• pp.57-64
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• 2008

In this paper, we propose a system-level simulator for the performance analysis of a Solid-State Disk (SSD) in PC environment by using TLM (Transaction Level Modeling) method. Our method provides quantitative analysis for a variety of architectural choices of PC system as well as SSD. Also, it drastically reduces the analysis time compared to the conventional RTL (Register Transfer Level) modeling method. To show the effectiveness of the proposed simulator, we performed several explorations of PC architecture as well as SSD. More specifically, we measured the performance impact of the hit rate of a cache buffer which temporarily stores the data from PC. Also, we analyzed the performance variation of SSD for various NAND Flash memories which show different response time with our simulator. These experimental results show that our simulator can be effectively utilized for the architecture exploration of SSD as well as PC.

• Journal of the Institute of Convergence Signal Processing
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• v.10 no.2
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• pp.141-145
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• 2009

A C-to-SystemC synthesizer which processes the input behavior according to high-level synthesis, and then transforms the synthesis result into SystemC module code is implemented in this paper. In the synthesis process, the input behavioral description in C source code is scheduled using list scheduling algorithm and register allocation is performed using left-edge algorithm on the result of scheduling. In the SystemC process, the output from high-level synthesis process is transformed into SystemC module code by combining it with SystemC features such as channels and ports. The operation of the implemented C-to-SystemC synthesizer is validated through simulating the synthesis of elliptic wave filter in SystemC code. C-to-SystemC synthesizer can be used as a part of tool-chain which helps to implement SystemC design methodology covering from modeling to synthesis.

• Journal of KIISE:Computer Systems and Theory
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• v.32 no.7
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• pp.359-367
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• 2005

This paper presents a scheduling approach for synthesizing pipelined datapaths under resource constraints. The proposed approach evaluates whether or not a scheduling solution can exist in case an operation temporarily is assigned to the earliest or latest control step among the assignable steps for the operation. If a solution cannot be found, it is impossible to assign the operation to that control step due to a violation against resource constraints, and so we can eliminate that control step among candidate assignable control steps. The proposed algorithm builds up a schedule based on gradual mobility reduction and finds a solution that yields high performance by evaluating on the impact on register assignment. Experiments on benchmarks show that this approach gains a considerable improvement over previous approaches.