• Asia-pacific Journal of Multimedia Services Convergent with Art, Humanities, and Sociology
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• v.7 no.2
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• pp.227-236
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• 2017

Quantum-dot cellular automata(QCA) consists of nano-scale cells and demands very low power consumption so that it is one of the alternative technologies that can overcome the limits of scaling CMOS technologies. Various circuits on QCA have been researched until these days, a latch required for counter and state control has been proposed as a component of sequential logic circuits. A latch uses a feedback loop to maintain previous state. In QCA, a latch uses a square structure using 4 clocks for feedback loop. Previous latches have been proposed using many cells and clocks in coplanar. In this paper, in order to eliminate these defects, we propose a SR and D latch using multilayer structure on QCA. Proposed three dimensional loop structure is based on multilayer and consists of 3 layers. Each layer has 2 clock differences between layers in order to reduce interference. The proposed latches are analyzed and compared to previous designs.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2005.07a
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• pp.178-179
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• 2005

ESD(Electrostatic Discharge) 보호에 응용되는 소자는 ESD가 발생했을 때, 빠르게 턴-온되어 외부로부터 EOS(Electric OverStress)를 차단함으로서 집적회로 내부의 코어를 보호해 주어야 한다. 이러한 기능에 충실한 LVTSCR(Low-Voltage Silicon Controlled Rectifier)은 트리거링 전압을 기존의 SCR보다 낮추어 ESD에 대해 민감한 반응을 할 수 있도록 개선한 소자이다. 그러나 트리거링 전압을 낮추면서 래치업 전압 또한 낮아지는 특성이 trade-off 관계로 맞물려 있어, LVTSCR의 단점인 낮은 래치업 전압을 효과적으로 다루는 것이 큰 이슈가 되고 있다. 본 논문에서는 LVTSCR의 ESD 보호에 대한 응용시 발생 가능한 래치업을 차폐하는 회로적 방법을 제시하였다. 제시된 새로운 구조의 차폐회로는 LVTSCR에서 래치업이 발생했을 때, 천이 전류를 감지하여 래치업이 발생되는 소자에 대한 전원을 스스로 차폐시켜 래치업에 대한 안정성을 시뮬레이션으로 검증하였다.

• Proceedings of the IEEK Conference
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• 1998.06a
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• pp.445-448
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• 1998

본 논문은 triple-well과 twin-well에서의 고에너지 이온주입 에너지와 도즈량 변화에 따른 래치업 특성을 비교하였다. 공정시뮬레이터인 ATHENA로 소자를 제작하고 도핑프로파일 형태와 구조를 조사한 후, 래치업 특성은 소자 시뮬레이터인 ATLAS를 이용하였다. triple-well 공정이 마스크 스텝수를 줄이고, 이온주입 후 열처리시간을 단축하며 별도의 열처리 공정없이 도핑르로파일을 넓은 형태로 분포시켜 래치업 면역특성이 매우 좋은 결과를 얻었다.

• Journal of the Korean Institute of Telematics and Electronics D
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• v.35D no.9
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• pp.54-61
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• 1998

A new Triple well structure is proposed for improved latch-up immunity at deep submicron CMOS device. Optimum latch-up immunity process condition is established and analyzed with varying ion implantation energy and amount of dose and also compared conventional twin well structure. Doping profile and structure are investigated using ATHENA which is process simulator, and then latch-up current is calculated using ATLAS which is device simulator. Two types of different process are affected by latch-up characteristics and shape of doping profiles. Finally, we obtained the best latch-up immunity with 2.5[mA/${\mu}{m}$] trigger current using 2.5 MeV implantation energy and 1$\times$10$^{14}$ [cm$^{-2}$ ] dose at p-well

• Proceedings of the KIEE Conference
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• 2004.11a
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• pp.17-19
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• 2004

트렌치 게이트 구조를 통해 순방향 전압 강하 손실 없이 기생 사이리스터 래치-업을 억제시키는 새로운 수평형 절연 게이트 바이폴라 트랜지스터 (LIGBT)를 제안하였다. 제안된 소자의 베이스 션트 저항은 정공의 우회로 인하여 감소하였으며, 이에 따라 기생 사이리스터 래치-업이 억제되었다. 제안된 소자의 순방향 전압강하는 트렌치 구조에 의한 유효 채널 폭 증가로 감소하였다. 제안된 소자의 동작 원리 분석을 위해 ISE-TCAD를 이용한 3차원 시뮬레이션을 수행하였으며, 표준 CMOS 공정을 이용하여 소자를 제작 및 측정하였다. 제안된 소자의 순방향 전압 강하는 기존의 LIGBT에 비해 증가하지 않았으며, 래치-업 용량은 2배로 향상되었다. 제안된 소자의 포화 전류는 감소하였으며, 이로 인하여 소자의 강인성 (ruggedness)이 향상되었다.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.43 no.9 s.351
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• pp.1-9
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• 2006

In the System-on-Chip(SoC) design, the global wires are critical parts for the performance. Therefore, the global wires need to be pipelined using flip-flops or latches. Since the timing constraint of the latch is more flexible than it of the flip-flop, the latch-based design can provide a better solution for the clock period. Retiming is an optimizing technique which repositions memory elements in the circuits to reduce the clock period. Traditionally, retiming is used on gate-level netlist, but retiming for SoC is used on macro-level netlist. In this paper, we extend the previous work of retiming for SoC using flip-flops to retiming for SoC using single-phase clocked latches. In this paper we propose a MILP for retiming for SoC using single-phase clocked latches, and apply the fixpoint computation to solve it. Experimental results show that retiming for SoC using latches reduces the clock period of circuits by average 10 percent compared with retiming for SoC using flip-flops.

• Journal of the Microelectronics and Packaging Society
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• v.24 no.3
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• pp.41-46
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• 2017

In this study, rapid cooling method was proposed to improve the anti-scratch performance of anti-reflection film fabricated by nanoimprint lithography. Effects of cooling time on the mechanical properties and optical properties were evaluated. Pencil hardness measurements showed that anti-scratch performance enhanced as the cooling time increased while characterization on the optical property showed that reflectance on scratch increased as the cooling time increased. Therefore, it was concluded that the anti-scratch performance and optical properties are highly influenced by the cooling time. The observed results explained in terms of residual stress and free volume in polymeric materials.

• Transactions of the Korean Society for Noise and Vibration Engineering
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• v.14 no.4
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• pp.287-294
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• 2004

Dynamic Load/unload (L/UL) mechanism is an alternative to the contact start stop (CSS) technology which eliminates striction and wear failure modes associated with CSS. Inertia latch mechanism becomes important for mobile disk drives because of non operating shock performance. Various types of latch designs have been introduced in hard disk drives to limit a rotary actuator from sudden uncontrolled motion. In this paper, a single spring inertia latch is introduced for a small form optical disk drive, which uses a rotary actuator for moving an optical pick-up. A new small inertia latch with sin91e spring is designed to ensure both feasible and small size. The shock performance of the new inertia latch is experimentally verified.

• Proceedings of the IEEK Conference
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• 1998.06a
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• pp.347-350
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• 1998

차세대 CMOS 구조에서 래치업 최소화를 위하여 고에너지 이온주입을 이용한 retrograde well 과 매몰층의 최적 공정 설계 변수 값들을 설정하였다. 본 논문에서는 두 가지의 모듸 모델 구조를 제안하고 silvaco 틀에 의한 시뮬레이션 결과를 비교 분석하엿다. 첫 번째 모델은 매몰층과 retrograde well을 조합한 구조이며, p+ injection trigger current가 600.mu.A/.mu.m 이상의 결과를 얻었고, 두번째 모델은 twin retrograde well을 이용하여 p+ injection 유지전류가 2500.mu.A/.mu.m이상의 결과를 얻었다. 시뮬레이션 결과, 두 모델 모두 도즈량이 많을수록 래치업 면역 특성이 좋아짐을 보았다. 시뮬레이션 조건에서 두 모델 모두 n+/p+ 간격은 2..mu.m 로 고정하였다.

• Journal of the Korean Society of Manufacturing Process Engineers
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• v.14 no.5
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• pp.102-106
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• 2015

In this paper, we study the optimal design for improved rotation latch system performance. The factors affecting the Torque generated in the armature were chosen as design variables. Utilizing the vertical matrix, the orthogonal array table was created to predict the results through minimal analysis. To confirm the Torque generation amount, by utilizing the commercial electromagnetic analysis software MAXWELL, finite element analysis was performed. The approximation method and experimental design through the commercial PIDO tool PIAnO for optimal design and calculations were utilized to perform experiments using an optimization method with evolutionary algorithms. Using the approximation model, design factors were determined that can maximize the torque generated in the armature, and the simulation was performed.