• Title/Summary/Keyword: 라이저

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Design of Riser in 1MW OTEC system mounted on Floating Barge (해상 부유식 1MW 해수온도차발전 시스템의 라이저 설계)

  • Kwon, YongJu;Jung, DongHo;Kim, HyeonJu
    • Journal of the Korean Society for Marine Environment & Energy
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    • v.18 no.1
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    • pp.22-28
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    • 2015
  • The design on a riser in 1MW OTEC system is performed. The minimum diameter of the riser is decided depending on intake quantity of deep-sea water to supply an OTEC cycle. An applicable pipe material is selected from analyzing the properties of commercial pipes. The selected HDPE pipe with the low density and strength is reinforced with a lumped block attached at the end of and wire ropes along the riser. A lumped block, connected to a floating structure by wire ropes, with 25% and 50% weight of a GFRP riser is designed to be attached the end of a riser. The structural safety of the HDPE riser with wire rope supporting axial loads induced by a lumped block is analyzed under the harsh ocean environmental condition near Hawaii ocean with the numerical method. The final dimension of the riser and accessories is determined considering the economic point of view. The designed riser will be applicable to the construction of the 1 MW OTEC pilot plant.

Conceptual Design of a Riser for 10 MW OTEC (10MW급 해양온도차발전을 위한 라이저 개념설계)

  • Jung, Dongho;Kwon, Yongju;Kim, Hyeonju
    • Journal of the Korean Society for Marine Environment & Energy
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    • v.18 no.1
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    • pp.29-35
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    • 2015
  • The concept design of a riser for Ocean Thermal Energy Conversion in 10 MW is proposed and its dynamic behaviour characteristics is analyzed with numerical method. A riser pipe with a hollow along its thickness in the cross-section to increase the effective modulus of its cross-section is designed considering the manufacture. The riser pipe without hollows along its thickness needs a lumped weight at the bottom end of a riser in order to keep its vertical hanging configuration from large buoyancy and the strong current. The riser is designed to control its density by inserting materials in high or low density into a hollow. The dynamic behaviour characteristics of the two designed risers is evaluated with the developed numerical analysis tool. The combined stress of the riser with a lumped weight is showed to be dominated by weight of a lumped mass. The riser with no hollow shows large combined stress near sea surface by strong current. Local structural analysis for the cross-section of a hollow riser is needed in detail.

라이신 수준이 재래흑돼지 냉동육의 저온저장중 품질특성에 미치는 영향

  • Gang, Seon-Mun;Kim, Yong-Seon;Gang, Chang-Gi;Chae, Byeong-Jo;Lee, Seong-Gi
    • Proceedings of the Korean Society for Food Science of Animal Resources Conference
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    • 2005.10a
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    • pp.250-254
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    • 2005
  • 본 연구는 육성기, 비육기 사료내 라이신 수준이 재래흑돼지 냉동육의 저온저장중 품질특성에 미치는 영향을 구명하고자 실시하였다. 드립감량은 재래흑돼지육이 개량종 돈육보다 낮았으며(p<0.05), TBARS는 저장 7일에 저라이신 수준의 개량종 돈육이 고라이신 수준의 개량종 돈육보다 높았으며(p<0.05), 저장기간 동안 재래흑돼지육과 개량종 돈육간에 차이가 없었다. L 값은 저장5일부터 재래흑돼지육이 저라이신 수준의 개량종 돈육보다 높았고(p<0.05), a 값은 재래흑돼지육이 개량종 돈육보다 유의적으로 높았다(p<0.05). b 값은 재래흑돼지육이 고라이신 수준의 개량종 돈육보다 높았다(p<0.05). 포화지방산은 저라이신 수준의 재래흑돼지육이 가장 높았으나(p<0.05), 불포화지방산과 불포화지방산/포화지방산 비율은 가장 낮았다(p<0.05). 단가불포화지방산/포화지방산 비율은 저라이신 수준의 재래흑돼지육이 고라이신 수준의 개량종 돈육보다 유의적으로 낮았다(p<0.05). 따라서 이상의 결과를 종합해 보면 재래흑돼지육이 개량종 돈육보다 보수력, 육색이 우수하였으며, 저라이신 수준의 사료를 급여시 재래흑돼지육의 포화지방산은 증가하였으나 불포화지방산은 감소하였다.

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A Variable-Q Digital Graphic Equalizer with Opposite Filters (Opposite 필터를 적용한 가변 Q 디지털 그래픽 이퀄라이저)

  • 이용희;김인철;조국춘
    • Journal of the Institute of Electronics Engineers of Korea SP
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    • v.41 no.4
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    • pp.131-139
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    • 2004
  • This paper proposes a variable-Q digital graphic equalizer with the opposite filters. A method for designing the proposed equalizer is also presented. In the proposed variable-Q equalizer, we adjust the Q-factor of the equalizer filter depending on the gain, yielding an improved equalizer performance. Also, by increasing the Q-factor of the opposite filters gracefully as the gain becomes greater, the inter-band interference can be removed effectively. We shall show that the frequency response of the proposed equalizer can reproduce the user's gain setting faithfully.

Implementation of Parallel Processing Interpolation Algorithm for Multicore GPU (다중코어 GPU를 위한 병렬처리 보간 알고리즘 구현)

  • Lee, Kwang-Yeob;Kim, Chi-Yong
    • Journal of IKEEE
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    • v.16 no.4
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    • pp.304-309
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    • 2012
  • As resolution for displays is recently more and more increasing, the amount of data abd calculation that graphic hardware needs to process are also increasing. Especially the amount of data processing by rasterizer is rapidly increasing. This paper used an algorism using coordinates in center of gravity and area for triangle instead of using bilinear algorism[1] used by conventional interpolation, which is to make it easier for parallel processing by rasterizer. This paper implemented designed rasterizer under FPGA environment, and compared it with conventional rasterizer and verified it. This rasterizer is proved to have approximately 50% higher performance compared to conventional one.

A Design on Rasterizer for the verification in a 3D Graphic Processor (3D 그래픽 프로세서 검증을 위한 래스터라이저 설계)

  • Lee, Mi-Kyoung;Jang, Young Jo
    • Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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    • 2009.10a
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    • pp.639-642
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    • 2009
  • When the graphics accelerator for high-quality multimedia content design, hardware verification environment, easy and accurate performance evaluation in an embedded device is required. To work around this is not verified through the simulation waveform analysis to determine the actual calculated graphic images has designed a software rasterizer. Rasterizer is designed for Windows-based environment using the C language implementation of rasterization has a function at each step. Vertex data is entered and the results were verified.

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A study on the hearing characteristic based equalizer design for the elderly (고령층의 가청주파수 특성을 고려한 이퀄라이저 연구)

  • Lee, Chul-Hee;Hong, Sung-Kyoo
    • Journal of Digital Contents Society
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    • v.19 no.4
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    • pp.779-787
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    • 2018
  • This study delves into how the equalizer can compensate for a sound pressure of lost frequencies. The targeted audiences are senior citizens who have difficulties hearing high-frequency because of a decline of audio frequency. Through investigations, this study confirms that the reason why reduction of high-frequency hearing increases depending on senescence. By considering the features of audio frequency of senior citizens, it also clarifies the necessity of equalizer reflecting features of audio frequency for the senior citizens, which have dramatically increased in Korea. There are application programs having functions, which provide several options of equalizer setup that people can adjust it depending on their own audio frequency. Some of them provide different equalizer setup depending on age. This study, however, reveals that they are not fully enough to compensate for the range of hearing loss of the senior citizens. Therefore, by pointing out limitations of existing functions and suggesting improvements, this study explores the way of improvements that enhance the sound transmissions of digital media contents for senior citizens.

Nonlinear Dynamic Analysis of Deep Water Riser by the Utilization on the Kinematic Constraint Condition (운동학적 제약조건을 이용한 심해저 라이저의 비선형 동적해석)

  • 홍남식
    • Journal of the Computational Structural Engineering Institute of Korea
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    • v.12 no.3
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    • pp.495-508
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    • 1999
  • 변형된 라이저의 단위 접선벡터상의 운동학적 제약조건을 적용하여 심해저 라이저의 비선형 동적해석을 행한다. 이 조건의 적용으로 자유도수를 감소시킬 수 있으며 심한 비선형성으로 인한 해의 발산 가능성을 제거할 수 있다. 라이저의 거대변형으로 인한 기하학적 비선형성과 비선형 경계조건이 고려된다. 또한, 비선형성이 포함되는 수동학적 하중이 조류와 파랑에 의해 발생하여 내부에 정상류가 흐르는 라이저관의 외벽에 작용하게 된다. 이 외에도라이저 자체의 축방향 변형조건을 고려한다. Galerkin의 유한요소 근사화와 시간증분자를 적용하여 유한요소에 대한 평형 메트릭스 방정식을 유도하고, 수치해석을 위한 알고리즘을 제안하며 API 보고서의 결과와 비교함으로써 제안된 모델이 검증된다. 또한, 기하학적 비선형성으로 인한 영향을 조사하였다.

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A 12.5-Gb/s Low Power Receiver with Equalizer Adaptation (이퀄라이저 적응기를 포함한 12.5-Gb/s 저전력 수신단 설계)

  • Kang, Jung-Myung;Jung, Woo-Chul;Kwon, Kee-Won;Chun, Jung-Hoon
    • Journal of the Institute of Electronics and Information Engineers
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    • v.50 no.12
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    • pp.71-79
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    • 2013
  • This paper describes a 12.5 Gb/s low-power receiver design with equalizer adaptation. The receiver adapts to channel and chip process variation by adaptation circuit using sampler and serializer. The adaptation principle is explained. It describes technique receiving ground referenced differential signal of voltage-mode transmitter for low-power. The CTLE(Continuous Time Linear Equalizer) having 17.6 dB peaking gain to remove long tail ISI caused channel with -21 dB attenuation. The voltage margin is 210 mV and the timing margin is 0.75 UI in eye diagram. The receiver consumes 0.87 mW/Gb/s low power in 45 nm CMOS technology.