• Journal of the Korea Institute of Information and Communication Engineering
• /
• v.16 no.4
• /
• pp.799-804
• /
• 2012

To converter time information to digital information Time-to-Digital Converter(TDC) is designed by using analog delay elements. To obtain the temperature stable characteristics the circuit is designed and the operation of the designed circuit is confirmed by HSPICE. The characteristics variation of the designed delay element with temperature is from -0.18% to 0.126% compared to room temperature characteristics when the temperature is varied from $-20^{\circ}C$ tp $70^{\circ}C$. Time difference is from -0.18% to 0.12% compared to room temperature characteristic when the temperature is varied from $-20^{\circ}C$ tp $70^{\circ}C$. The time difference is simulated when the digital output is 15. However the time difference is from -1.09% to 1.28% in the TDC using temperature non-stable analog delay elements.

• Knowledge Management Research
• /
• v.24 no.3
• /
• pp.173-193
• /
• 2023

Digital transformation and the COVID-19 pandemic have facilitated the rapid development and dissemination of non-face-to-face technologies such as self-service technologies (SSTs). This research investigates how motivation factors affect consumers' negative responses to digital shadow work (DSW) in SSTs which decreases their continuous use intention of SSTs. Also, we examine whether the grafication delay ability moderates the relationship between consumers' negative responses to DSW and their continuous use intention of SSTs. By an analysis of usable 450 user respondents via SmartPLS 4.0, perceived benefits was found to significantly influence consumers' negative responses to DSW. Also, consumers' negative responses to DSW can significantly decrease their intention to continue using SSTs. Further, the effect of negative responses to DSW on continuous use intention of SSTs is stronger in case of consumers with low gratification delay ability than in case of consumers with high gratification delay ability. The study findings contribute to providing some strategies for companies operating SSTs by examining the effects of consumer's responses to DSW and gratification delay ability on the continuous usage intention of SSTs.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
• /
• 2011.05a
• /
• pp.671-672
• /
• 2011

Time to digital converter is designed. To obtain the digital signal from time information the analog delay element is used. Because the analog delay element shows more stable characteristics compared to the digital delay element in view point of process variation. The designed circuit has temperature stale characteristics when the range of operating temperature is from $-20^{\circ}C$ to $70^{\circ}C$. The circuit is simulated and confirmed by HSPICE.

• The KIPS Transactions:PartC
• /
• v.8C no.2
• /
• pp.164-172
• /
• 2001

최근 인터넷의 확산과 더불어 디지털 비디오 라이브러리(DVL : Digital Video Library) 서비스에 대한 관심이 고조되고 있다. 그러나 현재의 통신망 대역폭과 스위칭 환경 하에서는 종단간 QoS 보장하는데 많은 제약사항이 존재한다. 따라서 본 논문에서는 비디오 스트림 처리를 효율적으로 수행하여, 지연-처리율 특성을 만족할 수 있는 스트림 스위칭 구조를 제안하고 이에 대한 성능을 분석하였다. 제안된 ATM-기반 스트림 스위치는 각각 다중화되는 CBR(Constant Bit Rate) 및 VBR(Variable Bit Rate) 스트림의 QoS(Quality of Service)를 보장해야만 한다. 성능분석 결과는 제안된 스위치의 처리율이 r=4일 때 약 0.996의 값을 보였으며, 지연시간도 부하가 0.7 이하일 때 2미만으로 특정되었다. 이 결과는 제안된 구조가 적당한 입력 스트림의 그룹핑을 통하여 비디오 응용을 위한 처리율 및 지연 요구사항 QoS를 보장할 수 있음을 보여준다.

• Journal of the Institute of Electronics and Information Engineers
• /
• v.50 no.2
• /
• pp.122-133
• /
• 2013

An arbiter-based simple phase decision circuit (PDC) optimized for high-resolution phase-to-digital converter made up of an analog phase-frequency detector and a time-to-digital converter for all-digital phase-locked loops is proposed. It can distinguish very small phase difference between two pulses even though it consumes lower power and has smaller input-to-output delay than the previously reported PDC. Proposed PDC is realized using 130-nm CMOS process and demonstrated by transistor-level simulations. A 5-bit P2D having no offset nor deadzone using the PDC is also demonstrated. A harmonic-lock-free and small-phase-offset delay-locked loop for fixing the P2D resolution regardless of PVT variations is also proposed and demonstrated.

• The Optical Journal
• /
• s.121
• /
• pp.32-33
• /
• 2009

• The Journal of Korean Institute of Electromagnetic Engineering and Science
• /
• v.22 no.6
• /
• pp.577-583
• /
• 2011

Radar performance test is one of the major steps for radar system design. However, it is restricted by time and cost when radar performance tests are performed with opportunity targets. So various simulated target generators are developed and used to evaluate radar performance. To simulate the target's range, most of simulated target generators are developed with optical line or DRFM(Digital RF Memory) technique but there are many restrictions such as limit of range imitation and test scenario because of their original usage. In this paper, DDL(Digital Delay Line) module for development of simulated target generator is designed with precise range simulation and easily embodiment feature. And pulse recognition and delay gap detection technique are used to simulate the time delay without distortions. Developed DDL module performances are verified through their performance tests and test results are described in this paper.

• Journal of the Korea Institute of Information and Communication Engineering
• /
• v.4 no.2
• /
• pp.417-426
• /
• 2000

In this paper, CE-CPSK(Constant Envelope Continuous Phase Shift Keying) modulated DS/SS(Direct Sequence Spread Spectrum) transceiver with 908 MHz carrier frequency and 1.5 MHz PN clock rate is proposed. To overcome the effect of nun-linear power amplifier, CE-CPSK modulation method which has the constant envelope and continuous phase characteristics is proposed. To analyze the DS/SS receiver performance with respect to code tracking loop, multipath fading channel is characterized as a two-ray Rayleigh fading channel. To compensate the demerit of analog delay locked loop, digital delay locked loop is employed for code tracking loop. Simulation and experimental examination has been carried out in AWGN(Additive White Gaussian Noise) and Rayleigh fading channel environment in order to prove validity of the proposed method.

• Journal of Digital Contents Society
• /
• v.9 no.4
• /
• pp.679-686
• /
• 2008

Wireless LAN(WLAN) is a rather mature communication technology connecting mobile terminals. IEEE 802.11 is a representative protocol among WLAN technologies. With the rising popularity of delay-sensitive real-time multimedia applications(video, voice and data) in IEEE 802.11 wireless LAN, it is important to study the MAC layer delay performance of WLANs. In this paper, performance for packet delay model that recently have been proposed schemes is analysed in wireless LAN and proved performance results via simulation.

• Proceedings of the KIPE Conference
• /
• 2007.07a
• /
• pp.223-225
• /
• 2007

본 논문에서는 FPGA(Field Programmable Gate Array) 기반의 전류 제어기를 설계하고 구현하였다. 기존의 DSP (Digital Signal Processor) 기반의 전류 제어기는 알고리즘 연산으로 인해 일반적으로 한 샘플링의 디지털 시지연이 발생한다. 반면에, FPGA 기반의 전류제어기는 FPGA의 높은 연산 능력을 이용하여, 알고리즘 연산에 필요한 시간을 감소시킬 수 있다. 이는 시지연이 물리적으로 줄기 때문에, 어떠한 시지연 보상 알고리즘 없이 전류 제어기의 대역폭을 향상시킬 수 있다. 구현된 FPGA 기반의 전류 제어기의 성능은 실험을 통해 검증되었다.