• Title/Summary/Keyword: 디스페러티

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Environment Map Based Disparity (환경맵 기반 디스페러티)

  • Ryoo Seung-Taek
    • Journal of Korea Multimedia Society
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    • v.9 no.1
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    • pp.109-118
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    • 2006
  • In this paper, we suggest the environment based disparity method that calculate the depth value of the objects from environment maps. This method using the disparity of the environment map can calculate the depth value from two environment map that acquire at different viewpoint. This method can decide the visibility of the object whether it is occluded others or not. Also, we can analogize the depth value of the object that does not relate the reference plane(in case of being in the air) and make three dimensional environment model using the proposed method

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High Performance Coprocessor Architecture for Real-Time Dense Disparity Map (실시간 Dense Disparity Map 추출을 위한 고성능 가속기 구조 설계)

  • Kim, Cheong-Ghil;Srini, Vason P.;Kim, Shin-Dug
    • The KIPS Transactions:PartA
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    • v.14A no.5
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    • pp.301-308
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    • 2007
  • This paper proposes high performance coprocessor architecture for real time dense disparity computation based on a phase-based binocular stereo matching technique called local weighted phase-correlation(LWPC). The algorithm combines the robustness of wavelet based phase difference methods and the basic control strategy of phase correlation methods, which consists of 4 stages. For parallel and efficient hardware implementation, the proposed architecture employs SIMD(Single Instruction Multiple Data Stream) architecture for each functional stage and all stages work on pipelined mode. Such that the newly devised pipelined linear array processor is optimized for the case of row-column image processing eliminating the need for transposed memory while preserving generality and high throughput. The proposed architecture is implemented with Xilinx HDL tool and the required hardware resources are calculated in terms of look up tables, flip flops, slices, and the amount of memory. The result shows the possibility that the proposed architecture can be integrated into one chip while maintaining the processing speed at video rate.