• Title/Summary/Keyword: 동기제어 알고리즘

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Concurrency Control Using the Update Graph in Replicated Database Systems (중복 데이터베이스 시스템에서 갱신그래프를 이용한 동시성제어)

  • Choe, Hui-Yeong;Lee, Gwi-Sang;Hwang, Bu-Hyeon
    • The KIPS Transactions:PartD
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    • v.9D no.4
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    • pp.587-602
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    • 2002
  • Replicated database system was emerged to resolve the problem of reduction of the availability and the reliability due to the communication failures and site errors generated at centralized database system. But if update transactions are many occurred, the update is equally executed for all replicated data. Therefore, there are many problems the same thing a message overhead generated by synchronization and the reduce of concurrency happened because of delaying the transaction. In this paper, I propose a new concurrency control algorithm for enhancing the degree of parallelism of the transaction in fully replicated database designed to improve the availability and the reliability. To improve the system performance in the replicated database should be performed the last operations in the submitted site of transactions and be independently executed update-only transactions composed of write-only transactions in all sites. I propose concurrency control method to maintain the consistency of the replicated database and reflect the result of update-only transactions in all sites. The superiority of the proposed method has been tested from the respondence and withdrawal rate. The results confirm the superiority of the proposed technique over classical correlation based method.

Design and Performance Analysis of Multicarrier 16QAM System in Simulcast Fading Channel (동시전송 감쇠 채널에서 다중반송파 16QAM 시스템의 설계 및 성능분석)

  • Kim, Gyeong-Deok;Lee, Chang-Jae;Hwang, Seong-Hyeon;Choe, Hyeong-Jin
    • Journal of the Institute of Electronics Engineers of Korea TC
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    • v.37 no.10
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    • pp.26-36
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    • 2000
  • In this paper, we design the nonoverlapping multicarrier modulation (MCM) system for high rate paging system and evaluate the Performance by computer simulation. In conventional paging system, FSK was usually used, but we select QAM for high bandwidth efficiency. Transmitter structure adopts that of 4-16QAM of the iDEN$\^$TM/ and receiver consists of symbol timing recovery, carrier recovery and automatic gain control. In addition, pilot symbol aided modulation (PSAM) which can overcome the simulcast fading channel is considered and we also propose the optimum pilot symbol pattern. Finally, we show the performance of the overall 4-16QAM system by computer simulation.

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A Priority-based Feedback Control Mechanism for Scalability (확장적 우선 순위 피드백 제어 기법)

  • 정상운;정원창;김상복
    • Journal of Korea Multimedia Society
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    • v.2 no.3
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    • pp.339-346
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    • 1999
  • When a multicast video conference system utilizes RTP (Real Time Protocol) and RTCP (Real Time Control Protocol), the loss rate and the synchronization of transfer in RTCP affect the scalability of the system. The random delay technique introduced to resolve the problems is so simple that leads the network to meet some congestion in synchronizing feedback information when lots of people transfer the feedback information simultaneously, which reduces the scalability of system. In this paper, we propose a new feedback control algorithm that provides priority levels with the RTCP packet, which cuts down the feedback delay and increases the scalability. The criteria of providing priority Based on the decided priority level, Agent forced the session participants to provide much more RTCP packets, positively controlled, and the possible bandwidth can be measured. The simulation on this technique decreases the delay, and the feedback messages are equally distributed on a given time period.

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Topological Interference Management via 8 Trigram (8괘(卦)(Trigram)를 이용한 위상간섭 제거)

  • Lee, Moon Ho
    • The Journal of the Institute of Internet, Broadcasting and Communication
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    • v.17 no.4
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    • pp.95-106
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    • 2017
  • In this paper, we investigate the conventional topological interference management (TIM) with proposed network topology such as 8 trigram (8 user networks). The key observation is that optimal symmetric degree of freedom (DoF) can be achieved for 8 user network with different channel coherence times by adaptively selecting the interference alignment scheme via controlling the alignment feasibility of the transmitted signals. However, this yields a very complex problem, for which we use the combination of different schemes such as interference avoidance and repetition coding. In addition to the above schemes, we propose a triangular transmit cooperation (TTC) algorithm for 8 user networks to achieve the optimal symmetric DoF. And We apply the principle of complementarity of 8 trigram to remove the interferences, and correspond the concepts of win-win and conflict to direct and indirect signals of transmit and receive respectively. We find that the principle of complementarity comes out from the trigram of I Ching. That is, we apply the relation of confrontation and coexistence to 8 transmitters and receivers, and get the results of symmetric DoF of 4/3.

Algorithm for Switch Open Fault Detection of Asymmetric 6-phase PMSM Based on Stationary Reference Frame dq-axis Currents (비대칭 6상 영구자석 동기 전동기의 정지 좌표계 DQ축 전류를 이용한 스위치 개방 고장 검출 기법)

  • Lee, Won-Seok;Kim, Han-Eol;Hwang, Seon-Hwan;Lee, Ki-Chang;Park, Jong-Won
    • Journal of IKEEE
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    • v.26 no.2
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    • pp.265-270
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    • 2022
  • This paper proposes the detection algorithm for switch open fault of asymmetric 6-phase PMSM based on stationary reference frame dq-axis currents. In this paper, target motor has an asymmetric structure in which two upper three windings have an electrical phase difference of 30° and a neutral point is separated. As a result, dual 3-phase PWM inverters and the detection techniques due to open failures of switch are definitely required. In this paper, the dual dq-axis current control method is used for driving the asymmetric 6-phase PMSM and the open fault switch should be detected by using variable all pass filter and low pass filter in order to detect the current amplitude. The effectiveness and usefulness of the proposed method is verified by several experiments.

Development of 200kW class electric vehicle traction motor driver based on SiC MOSFET (SiC MOSFET기반 200kW급 전기차 구동용 모터드라이버 개발)

  • Yeonwoo, Kim;Sehwan, Kim;Minjae, Kim;Uihyung, Yi;Sungwon, Lee
    • Journal of IKEEE
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    • v.26 no.4
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    • pp.671-680
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    • 2022
  • In this paper, A 200kW traction motor driver that covers most of the traction motor specification of commercial electric vehicles (EV) is developed. In order to achieve high efficiency and high power density, a next-generation power semiconductors (Silicon carbide, SiC) are applied instead of power semiconductor(IGBT), which is Si based. Through hardware analysis for optimal use of SiC, expected efficiency and heat dissipation characteristics are obtained. A vector control algorithm for an IPMSM (Interior permanent magnet synchronous motor), which is mostly used in EV(Electric vehicle) traction motor, is implemented using DSP (Digital signal processor). In this paper, a prototype traction motor driver based SiC for EV is designed and manufactured, and its performance is verified through experiments.

Design of Digital Phase-locked Loop based on Two-layer Frobenius norm Finite Impulse Response Filter (2계층 Frobenius norm 유한 임펄스 응답 필터 기반 디지털 위상 고정 루프 설계)

  • Sin Kim;Sung Shin;Sung-Hyun You;Hyun-Duck Choi
    • The Journal of the Korea institute of electronic communication sciences
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    • v.19 no.1
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    • pp.31-38
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    • 2024
  • The digital phase-locked loop(DPLL) is one of the circuits composed of a digital detector, digital loop filter, voltage-controlled oscillator, and divider as a fundamental circuit, widely used in many fields such as electrical and circuit fields. A state estimator using various mathematical algorithms is used to improve the performance of a digital phase-locked loop. Traditional state estimators have utilized Kalman filters of infinite impulse response state estimators, and digital phase-locked loops based on infinite impulse response state estimators can cause rapid performance degradation in unexpected situations such as inaccuracies in initial values, model errors, and various disturbances. In this paper, we propose a two-layer Frobenius norm-based finite impulse state estimator to design a new digital phase-locked loop. The proposed state estimator uses the estimated state of the first layer to estimate the state of the first layer with the accumulated measurement value. To verify the robust performance of the new finite impulse response state estimator-based digital phase locked-loop, simulations were performed by comparing it with the infinite impulse response state estimator in situations where noise covariance information was inaccurate.

A Study on Teaching the Method of Lagrange Multipliers in the Era of Digital Transformation (라그랑주 승수법의 교수·학습에 대한 소고: 라그랑주 승수법을 활용한 주성분 분석 사례)

  • Lee, Sang-Gu;Nam, Yun;Lee, Jae Hwa
    • Communications of Mathematical Education
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    • v.37 no.1
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    • pp.65-84
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    • 2023
  • The method of Lagrange multipliers, one of the most fundamental algorithms for solving equality constrained optimization problems, has been widely used in basic mathematics for artificial intelligence (AI), linear algebra, optimization theory, and control theory. This method is an important tool that connects calculus and linear algebra. It is actively used in artificial intelligence algorithms including principal component analysis (PCA). Therefore, it is desired that instructors motivate students who first encounter this method in college calculus. In this paper, we provide an integrated perspective for instructors to teach the method of Lagrange multipliers effectively. First, we provide visualization materials and Python-based code, helping to understand the principle of this method. Second, we give a full explanation on the relation between Lagrange multiplier and eigenvalues of a matrix. Third, we give the proof of the first-order optimality condition, which is a fundamental of the method of Lagrange multipliers, and briefly introduce the generalized version of it in optimization. Finally, we give an example of PCA analysis on a real data. These materials can be utilized in class for teaching of the method of Lagrange multipliers.

FPGA-based One-Chip Architecture and Design of Real-time Video CODEC with Embedded Blind Watermarking (블라인드 워터마킹을 내장한 실시간 비디오 코덱의 FPGA기반 단일 칩 구조 및 설계)

  • 서영호;김대경;유지상;김동욱
    • The Journal of Korean Institute of Communications and Information Sciences
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    • v.29 no.8C
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    • pp.1113-1124
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    • 2004
  • In this paper, we proposed a hardware(H/W) structure which can compress and recontruct the input image in real time operation and implemented it into a FPGA platform using VHDL(VHSIC Hardware Description Language). All the image processing element to process both compression and reconstruction in a FPGA were considered each of them was mapped into H/W with the efficient structure for FPGA. We used the DWT(discrete wavelet transform) which transforms the data from spatial domain to the frequency domain, because use considered the motion JPEG2000 as the application. The implemented H/W is separated to both the data path part and the control part. The data path part consisted of the image processing blocks and the data processing blocks. The image processing blocks consisted of the DWT Kernel fur the filtering by DWT, Quantizer/Huffman Encoder, Inverse Adder/Buffer for adding the low frequency coefficient to the high frequency one in the inverse DWT operation, and Huffman Decoder. Also there existed the interface blocks for communicating with the external application environments and the timing blocks for buffering between the internal blocks The global operations of the designed H/W are the image compression and the reconstruction, and it is operated by the unit of a field synchronized with the A/D converter. The implemented H/W used the 69%(16980) LAB(Logic Array Block) and 9%(28352) ESB(Embedded System Block) in the APEX20KC EP20K600CB652-7 FPGA chip of ALTERA, and stably operated in the 70MHz clock frequency. So we verified the real time operation of 60 fields/sec(30 frames/sec).

Reducing Flooding Latency in Power Save Mode of IEEE 802.11-based Mobile Ad hoc Networks (IEEE 802.11 기반 이동 애드혹 망의 전력 절감 모드에서 플러딩 지연의 개선)

  • 윤현주;서명환;마중수
    • Journal of KIISE:Information Networking
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    • v.31 no.5
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    • pp.532-543
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    • 2004
  • Mobile Ad hoc NETworks (MANET) consist of mobile nodes which are usually powered by battery Approaches for minimizing power consumption have been proposed for all network layers and devices. IEEE 802.11 DCF (Distributed Coordination Function), a well-known medium access control protocol for MANETS, also defines a power save mode operation. The nodes in power save mode periodically repeat the awake state and the doze state in synchronized fashion. When all nodes are in the awake state, the exchange the announcements for the subsequent message transmission with neighbors. The nodes that send or receive the announcements stay awake for data transmission, and others go into the dole state. The previous works for enhancing the power save mode operation have focused on shortening the duration of the awake state. We observed that the longer sleeping period results in seriously long delivery latency and the consequent unnecessary power consumption as well, because the packets can move forward only one hop for a fixed interval. In this paper, we propose an improved protocol for the power save mode of IEEE 802.11 DCF, which allows the flooding packets to be forwarded several hops in a transmission period. Our approach does not reduce the duration of compulsory awake period, but maximizes its utilization. Each node propagates the announcements for next flooding to nodes of several hops away, thus the packets can travel multiple hops during one interval. Simulation results of comparison between our scheme and the standard show a reduction in flooding delay maximum 80%, and the unicasting latency with accompanying flooding flows near 50%, with slight increase of energy consumption.