• Journal of Educational Research in Mathematics
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• v.24 no.4
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• pp.623-644
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• 2014

Many researchers have supported in various aspects that elementary students should experience alternative algorithms as well as formal standard one for addition and subtraction. Korean elementary mathematics textbooks have some units for alternative algorithms for addition and subtraction. In special, the change of unit sequence in the second grade revised mathematics textbooks may cause the necessity for discussion about teaching sequence and teaching purpose between alternative algorithms and formal standard one. Therefore, this study aims to consider the purpose of teaching alternative algorithms and to induce implications for their teaching strategies and sequence. To do this, related references, curriculum and textbooks were analyzed. Four lessons were observed and three teachers were interviewed. The main content of this study is the result of analysis on students' activities and teachers'teaching approaches. This study also includes didactical implications based on the result.

• Journal of the Institute of Convergence Signal Processing
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• v.6 no.3
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• pp.134-142
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• 2005

The implementation of Multiple-Valued Logic(MVL) based on Current-Mode CMOS Logic(CMCL) circuits has recently been achieved. In this paper, four-valued Unary Multiple-Valued logic functions are synthesized using current-mode CMOS logic circuits. We properly make use of the fact that the CMCL addition of logic values represented using discrete current values can be performed at no cost and that negative logic values are readily available via reversing the direction of current flow. A synthesis process for CMCL circuits is based upon a logically complete set of basic elements. Proposed algorithm results in less expensive realization than those achieved using existing techniques in terms of the number of transistors needed. As an alternative to the cost-table techniques Universal Unary Programmable Circuit (UUPC) for a unary function is also proposed.