• Electronics and Telecommunications Trends
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• v.9 no.3
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• pp.69-96
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• 1994

본고에서는 캐시 동일성 유지 기법들을 분류하여 그 특성들을 개략적으로 살펴본 후 대규모 다중프로세서를 위해 제안된 것 중 몇몇 특색있는 것들을 살펴본다.

• The Magazine of the IEIE
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• v.18 no.7
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• pp.31-40
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• 1991

TICOM은 국내에서 독자적으로 설계, 개발한 수퍼미니급 컴퓨터 시스템이다. TICOM은 다중프로세서 구조에 UNIX를 기반으로 한 다중처리용 운영체제를 갖고 있다. 본 고는 한국전자통신연구소에서 개발한 행정전산망 주전산기 TICOM의 설계ROSUA, 시스템 구조와 특성을 살펴보고 시스템 성능에 대해 서술한다.

• Journal of KIISE:Computer Systems and Theory
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• v.27 no.6
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• pp.558-566
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• 2000

Object recognition is a challenging application for high-performance computing. Currently, the superscalar architecture dominates todays microprocessor marketplace. As more transistors are integrated onto larger die, however, an on-chip multiprocessor is regarded as a promising alternative to the superscalar microprocessor. This paper examines the behavior of the object recognition on the on-chip multiprocessor, which will be employed in general-purpose parallel machines. To obtain the performance characteristics of the microprocessor, a program-driven simulator and its programming environment were developed. The simulation results showed that the on-chip multiprocessor can exploit thread level parallelisms effectively and offer a promising architecture for the object recognition application.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.18 no.1
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• pp.97-102
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• 2014

Abdelzaher et al. proposed an algorithm to determine the schedulability of aperiodic tasks on multiprocessor systems, and proved that the aperiodic tasks are schedulable if the upperbound of synthetic utilization is less than or equal to 0.59. But this algorithm has a drawback in that if some tasks, even though they are completed and have no more execution times, are included in the current invocation set, their execution times and deadlines are added to the synthetic utilization. This may lead to a problem in which actually schedulable tasks are decided not to be schedulable. In this paper, we recognize the above mentioned problem and propose an improved synthetic utilization method that can be used to schedule aperiodic tasks more efficiently on multiprocessor systems.

• Journal of KIISE:Computer Systems and Theory
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• v.27 no.3
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• pp.337-344
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• 2000

In this paper, we define a Process Algebra ACSMR(Algebra of Communicating Shared Multiple Resources) for system specification and verification using multiple resources. ACSMR extends a concept of multiple resources in ACSR that is a branch of formal methods based on process algebra. We'll show that two specification and verification examples. One is the specification of system behavior in multiprocessor using EDF(Earliest-Deadline-First) which is a scheduling algorithm of a real-time system. The other is the specification of describing timing analysis and resources restriction in a super scalar processor using multiple ports registers.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2012.10a
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• pp.733-735
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• 2012

Real-Time Aperiodic Tasks Scheduling Using Synthetic Utilization on Multiprocessor Systems has a drawback in that if some tasks, even though they are completed and have no more execution times, are included in the current invocation set, their execution times and deadlines are added to the synthetic utilization. This may lead to a problem in which actually schedulable tasks are decided not to be schedulable. In this paper, we recognize the above mentioned problem and propose an improved synthetic utilization method that can be used to schedule aperiodic tasks more efficiently on multiprocessor systems.

• The KIPS Transactions:PartA
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• v.17A no.6
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• pp.259-264
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• 2010

In case of scheduling tasks with shared resources in multiprocessor systems, Global Earliest Deadline First (GEDF) algorithm, equally applied Earliest Deadline First (EDF) which runs scheduling with deadline criterion, makes schedulability decline because GEDF typically does not have a specific process in order to handle tasks with shared resources. In this paper, we propose Earliest Deadline First with Partitioning (EDFP) for tasks with shared resources which partitions a task into two kinds of subtasks that include critical sections to access to shared resources, gives their own deadline respectively and manages them. As a result of simulations, EDFP shows better performance than GEDF for tasks with shared resources since system load goes up and the number of processor increases.

• The KIPS Transactions:PartA
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• v.9A no.4
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• pp.511-518
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• 2002

Symmetric Multiprocessors (SMP) has emerged as an important and cost-effective platform for high performance parallel computing. Scheduling of parallel tasks and communications of SMP is important because the choice of a scheduling discipline can have a significant impact on the performance of the system. In this paper, we present a task duplication based scheduling scheme for bus-based SMP. The proposed scheme pre-allocates network communication resources so as to avoid potential communication conflicts. The performance of the proposed scheme has been observed by comparing the schedule length under various number of processors and the communication cost.

• Proceedings of the Korea Society for Simulation Conference
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• 1998.10a
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• pp.161-165
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• 1998

다중 프로세서 구조로 실시간 분산 처리를 하는 전전자 교환기 시스템은 그 특성상 2개 이상의 프로세서에 동일한 값을 유지하는 중복 데이터의 사용이 필수적이다. 시스템의 자원 정보, 번호 번역 정보, 과금 정보 등이 중복 데이터로 사용된다. 이러한 중복 데이터에 대한 변경은 불일치 상태를 회피하기 위해 그 처리에 많은 비용과 제한이 따른다. 과도한 시그널 전송 및 로그 저장, 재전송 알고리즘은 데이터베이스 시스템의 성능을 저하시키고 때때로 순간적인 마비 상태까지도 유발할 수 있다. 본 논문에서는 기존 일관성 방안의 문제점을 분석하고 단일-버스 다중-프로세서 시스템에서 각각의 캐쉬들간의 일관성 유지를 위한 write-through 캐쉬 일관성 프로토콜을 사용하여 저 비용이며 효율적인 중복 데이터 일관성 유지 방안을 제시한다.

• The Transactions of the Korea Information Processing Society
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• v.7 no.10
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• pp.3049-3054
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• 2000

In this paper, the effects of the hardware components and runtime environments on the overall performance of a distributed shared memory system are analyzed through simulation. In simulation, the system is modeled using PARSE[1.2] closely to the real runtime environment and the 2D FFT is virtually executed on it. The results of simulation show that the minor hardware components such as bus interfaces and local bus of a processor, which are usuallyignored or neglected when analyzing performance. have significant impacts on the overall system performance. Performance variations caused from runtime environments such as loop overhead and code optimuzatio are also analyzed quantitatively.