• Journal of the Institute of Electronics Engineers of Korea CI
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• v.37 no.6
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• pp.1-9
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• 2000

This paper presents a Cluster Oriented Multistage Interconnection Network called COMR. COMR can be constructed suitable for the parallel application with localized communication by providing the shortcut path inside the processor-memory cluster which has frequent data communication. We evaluate the performance of COMR with respect to probability of acceptance, bandwidth, cost-effectiveness and average distance under varying degrees of localized communication. According to the result of analysis for performance evaluation, COMR shows higher performance than the regular MINs of the same network size in the highly localized communication. In the worst case, the diameter of an N$\times$N COMR is only n+1 which has only one stage more as compared the MIN with the same network size. Therefore COMR can be used as an attractive interconnection network for parallel applications with not only the localized communication distribution but also the uniform distribution in shared-memory multiprocessor system.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.19 no.5
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• pp.959-970
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• 1994

In this thesis, a printed score is read by using handy scanner and the recognition process is excuted in parallel, finally, on Mesh-Connected Computer. What is read is classified into certain patterns and is recognized, based on knowledge. The preprocessing steps are minimized and simple operations are used in the algorithm proposed in this thesis. The score symbols on a printed score can be recognized irrespective of their sizes but their diversity males it difficult to recognize them all, so it is programmed so as to recognize some symbols that is used necessarily and frequently. The recognized result is transformed into the MIDI standard file format. It is required to use a parallel processing system with multiprocessors because the high speed image processing is required. A digitized two-dimensional image is appropriate in processing on the SIMD Mesh-Connected Computer(MCC). Therefore, we explain this architecture and present parallel algorithm using SIMD MCC with n processors that achieves time complexity0(n).

• The Journal of Korean Institute of Communications and Information Sciences
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• v.27 no.10C
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• pp.963-972
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• 2002

An 8192-point pipelined FFT/IFFT processor core is designed, which can be used in multi-carrier modulation systems such as DUf-based VDSL modem and OFDM-based DVB system. In order to improve the signal-to-quantization-noise ratio (SQNR) of FFT/IFFT results, two-step convergent block floating-point (TS_CBFP) scaling is employed. Since the proposed TS_CBFP scaling does not require additional buffer memory, it reduces memory as much as about 80% when compared with conventional CBFP methods, resulting in area-and power-efficient implementation. The SQNR of about 60-㏈ is achieved with 10-bit input, 14-bit internal data and twiddle factors, and 16-bit output. The core synthesized using 0.25-$\mu\textrm{m}$ CMOS library has about 76,300 gates, 390K bits RAM, and twiddle factor ROM of 39K bits. Simulation results show that it can safely operate up to 50-㎒ clock frequency at 2.5-V supply, resulting that a 8192-point FFT/IFFT can be computed every 164-${\mu}\textrm{s}$. It was verified by Xilinx FPGA implementation.

• Journal of KIISE:Computer Systems and Theory
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• v.29 no.2
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• pp.105-115
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• 2002

Since NUMA architecture has to access remote memory an interconnection network determines the performance of CC-NUMA system Bus which has been used as a popular interconnection network has many limits to build a large-scale system because of the limited physical scalabilty and bandwidth Dual ring interconnection network composed of high speed point-to-point links is made up for resolving the defects of the bus for large-scale system But it also has a problem that the response latency is rapidly increased when many node are attached to snooping based CC-NUMA system with dual ring In this paper we propose a chordal ring architecture in order to overcome the problem of the dual ring on snooping based CC-NUMA system and design and efficient link controller adopted to this architecture. We also analyze the effects of chordal ring architecture on the system performance and the response latency by using probability driven simulator.

• The Journal of the Korea institute of electronic communication sciences
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• v.8 no.1
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• pp.199-206
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• 2013

Recently, the diverse needs of the drivers for in-vehicle infotainment systems are increasing rapidly. As a result, the infotainment systems are equipped with more convenient and human-friendly high-tech features. In this paper, we designed and implemented in-vehicle multimedia infotainment system based on embedded system that was applied various multimedia to in-vehicles. The proposed system can support independent display on each screen for the multi-channel multimedia source based on one processor(1 CPU). Therefore, our system can be reduced costs compared to other systems. This system not only displays the video and audio data in storage devices but also displays CAM, T-DMB, and DVB-T multimedia contents which are supplied in real-time services. Also, our system could multi-screen displays multimedia data in smart phone using Wi-Fi. We expect that in-vehicle infotainment systems like AVN(Audio video navigation) and RSE(Rear Seat Entertainment) could be used in various applications and reduced costs.

• Journal of the Institute of Electronics Engineers of Korea CI
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• v.40 no.4
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• pp.214-221
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• 2003

This paper shows an implementation of video codec (coder/decoder) on an embedded system. The video codec supports both H.261 and H.263 standards. For efficient real-time processing, the video codec is partitioned into a software module and a hardware module. Both modules are codesigned on an embedded system. The software module is processed on a real-time operating system and a RISC processor. It cooperates with the hardware module to compress and decompress images in real time. AMBA (Advanced Microcontroller Bus Architecture) AHB (Advanced High-performance Bus) is used as the system bus. The hardware module works both as AHB masters and as AHB slaves. The encoder part of the hardware module operates in a pipelines mode to compress images in real time. The video codec compresses 15 CIF frames and simultaneously decompresses 15 CIF frames in a second according to H.261 or H.263 standard at 33 MHz frequency.

• Journal of KIISE:Computer Systems and Theory
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• v.31 no.11
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• pp.643-657
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• 2004

The chordal ring based CC-NUMA system contains many links to transmit transactions between a local node and a remote node because of its structural characteristics. However, the inclination that the transactions concentrate on the ring link increases both the traffic of the ring link and the response time, which degrades the overall performance of the chordal ring based CC-NUMA system. In this paper we suggest a new remote cache replacement policy that considers both the number of total links and the number of ring links to traverse for the transactions. Our proposed replacement policy can balance data between the ring link and the chordal link properly because it reflects the characteristics of chordal ring based CC-NUMA system well.

• The Transactions of the Korea Information Processing Society
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• v.4 no.11
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• pp.2914-2922
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• 1997

For FA (factory automation) and ATE (automatic test equipment) in the industrial area, the standard bus needs to increase the system performance of multiprocessor environment. VME(versa module european package format) bus is appropriated to the standard bus but has features of small package and low board density. Beside, the density of board and semiconductor have grown to become significant issues that affect development time, project cost and field diagnostics. To fit this trend, in this paper, we composed Revision C.1 (IEEE std. P1014-1987) of the integrated environment for the main function such as arbitration, interrupt and interface between, VMEbus and several control modules Also the designed, VME system controller is implemented on FPGA that can be located even into slot 1. The control and function modules are coded with VHDL mid-fixed description method and then those operations are verified by simulation. As a result of experiment, we confirmed the most important that is the operation of Bus timer about Bus error signal should occur within $56{\mu}m$, and both control and function modules have the reciprocal operation correctly. Thus, the constructed VHDL library will be able to apply the system based VMEbus and ASIC design.

• Journal of the Korean Society for Aeronautical & Space Sciences
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• v.31 no.9
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• pp.94-102
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• 2003

This paper describes the development and implementation for the SYMBOLGEN(SYMBOL GENerator) software. The SYMBOL-GEN software is for improving graphic processing speed and decreasing data communication load in ASC by genera ting and downloading off-line symbol file for HUD and MFD , which are the main display equipments in military aircraft. The SYMBOL-GEN is developed on PC using C++ language and MS Visual Studio 6.0 development tool. It is also designed to be modified and extended easily by introducing object-oriented software development technique.

• Journal of the Korean Institute of Telematics and Electronics B
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• v.30B no.2
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• pp.33-43
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• 1993

Lock mechanism is essential for synchronization on the multiprocessor systems. Lock mechanism needs to reduce the time for lock operation in low lock contention. Lock mechanism must consider the case of the high lock contention. The conventional lock control scheme in memory results in the increase of bus traffic and memory utilization in lock operation. This paper suggests a lock scheme which stores the lock data in cache and manages it efficiently to reduce the time spent in lock operation when the lock contention is low on a multiprocessor system built on HiPi-bus(Highly Pipelined bus). This paper also presents the design of the HIPi-CLOCK (Highly Pipelined bus Cache LOCK mechanism) which transfere the data from on cache to another when the lock contention is high. The designed simulator compares the conventional lock scheme which controls the lock in memory with the suggested HiPi-CLOCK scheme in terms of the RMW(Read-Modify-Write) operation time using simulated trace. It is shown that the suggested lock control scheme performance is over twice than that of the conventional method in low lock contention. When the lock contention is high, the performance of the suggested scheme increases as the number of the shared lock data increases.