• Journal of KIISE
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• v.43 no.11
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• pp.1216-1222
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• 2016

The advent of large-scale web services has resulted in gradual increase in the amount of data used in those services. These big data are managed efficiently by DBMS such as MySQL and MariaDB, which use InnoDB engine as their storage engine, since InnoDB guarantees ACID and is suitable for handling large-scale data. To improve I/O performance, InnoDB caches data and index of its database through a buffer pool. It also supports multiple buffer pools to mitigate lock contentions. However, the multiple buffer pool scheme leads to the additional data consistency overhead. In this paper, we analyze the overhead of the multiple buffer pool scheme. In our experimental results, although multiple buffer pool scheme mitigates the lock contention by up to 46.3%, throughput of DMBS is significantly degraded by up to 50.6% due to increased disk I/O and fsync calls.

• Journal of the Institute of Electronics Engineers of Korea CI
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• v.47 no.1
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• pp.30-40
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• 2010

The hard disk is one of the most frequently used storage in IPTV sep-top box. It has large storage capacity and provides fast I/O speed compared to its price whereas it causes high power consumption due to mechanical characteristics of spindle motor. In order to play streaming data in the set-top box, spindle motor of hard disk keeps active mode and it causes high power consumption. In this paper, We propose an offset-buffering and multi-mode spin-down method to reduce power consumption for streaming data playback. The offset-buffering inspects the user's viewing pattern and performs buffering based on the analysis of viewing pattern. So, it can maintain the status of spindle motor as idle mode for long time. Besides, it can reduce power consumption by spinning down according to offset-buffer size. The experimental result shows that proposed offset-buffering and multi mode spin-down method is about 28.3% and 12.5% lower than the full-Buffering method in terms of the power consumption and spin-down frequency, respectively.

• Journal of the Institute of Electronics Engineers of Korea SC
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• v.46 no.2
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• pp.72-77
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• 2009

In this paper, a 3.2Gb/s clock and data recovery (CDR) circuit for a high-speed serial data communication without the reference clock is described This CDR circuit consists of 5 parts as Phase and frequency detector(PD and FD), multi-phase Voltage Controlled-Oscillator(VCO), Charge-pumps (CP) and external Loop-Filter(KF). It is adapted the PD and FD, which incorporates a half-rate bang-bang type oversampling PD and a half-rate FD that can improve pull-in range. The VCO consists of four fully differential delay cells with rail-to-rail current bias scheme that can increase the tuning range and tuning linearity. Each delay cell has output buffers as a full-swing generator and a duty-cycle mismatch compensation. This materialized CDR can achieve wide pull-in range without an extra reference clock and it can be also reduced chip area and power consumption effectively because there is no additional Phase Locked- Loop(PLL) for generating reference clock. The CDR circuit was designed for fabrication using 0.18um 1P6M CMOS process and total chip area excepted LF is $1{\times}1mm^2$. The pk-pk jitter of recovered clock is 26ps at 3.2Gb/s input data rate and total power consumes 63mW from 1.8V supply voltage according to simulation results. According to test result, the pk-pk jitter of recovered clock is 55ps at the same input data-rate and the reliable range of input data-rate is about from 2.4Gb/s to 3.4Gb/s.