• Korean Journal of Logic
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• v.14 no.1
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• pp.1-23
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• 2011

I take the position of the thirders on the sleeping beauty problem like Elga and criticize Lewisian halfers. In particular, I attack Franceschi's recent arguments for the halfers. In addition, I claim that Bostrom's and Kim's hybrid view is not satisfactory, because it is to pre-empt or to take the burden of proof that the problem is the genuine paradox. Consequently, the purpose of this paper is to show that the thirders' argument is more intuitive than others and what the fallacies of the halfer's arguments are.

• Proceedings of the Korean Information Science Society Conference
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• 2005.07a
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• pp.460-462
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• 2005

본 논문은 통신 시스템에서 오류 검출을 위해 널리 사용되고 있는 Cyclic Redundancy Check (CRC)회로의 병렬 구현을 위한 최적화 알고리즘을 제시한다. 논리 단을 최소로 하면서 가능한 않은 공유 텀을 찾아 매핑 함으로써 속도 및 게이트 수를 줄인다. 본 논문에서는 이더넷의 32비트 CRC를 병렬로 구현하여 성능평가를 하였다. FPGA 및 표준 셀 라이브러리를 이용하여 합성하였으며, 기존의 방식에 비해 속도와 면적 모두 향상되었음을 보여준다.

• Korean Journal of Logic
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• v.9 no.1
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• pp.137-171
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• 2006

베나세라프의 수의 비고유성 논증은 플라톤주의에 대한 강력한 반박들 중의 하나다. 이에 대한 플라톤주의 진영에서의 대응은 현재까지 네 가지 정도가 있었다. 라이트와 헤일로 대표되는 신프레게주의, 샤피로의 ante rem 구조주의, 밸러거의 혈기왕성한 플라톤주의, 그리고 잴타의 원리화된 플라톤주의에서의 대응들이 그것들이다. 이 네 가지 대응들 중 잴타의 원리화된 플라톤주의는 진정한 플라톤주의로 간주되기 매우 힘들며, 신프레게주의는 수의 비고유성 문제해결에 심각한 어려움을 갖고 있다. 한편 수의 비고유성 문제를 어느 정도 극복하고 있는 듯이 보이는 샤피로와 밸러거의 견해들 중, 밸러거의 견해는 인식과 지칭의 문제와 관련하여 심각한 난관에 봉착해 있다. 따라서 현재까지 제시된 이론의 상태에서는 샤피로의 견해가 수의 비고유성 문제를 인식의 문제와 함께 가장 잘 해결하고 있는 것으로 평가될 수 있다.

• Korean Journal of Logic
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• v.9 no.1
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• pp.97-136
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• 2006

비트겐슈타인의 규칙따르기 개념에 대한 올바른 이해는 그의 후기 철학의 궤적을 살피는데 있어서 중요하다. 비트겐슈타인의 규칙따르기 문제에 대해 회의적 해석으로 유명한 크립키는 "탐구"의 201절을 문제 삼으며 '역설'의 문제를 새로운 형식의 철학적 회의주의로 간주했다. 본 논문은 규칙의 역설에 대한 크립키의 논증이 비트겐슈타인의 관점과 무엇 때문에 충돌하는지를 밝히면서 그와 함께 비트겐슈타인이 '규칙의 역설'을 제시한 궁극적 이유를 규명하는데 있다. 규칙의 역설에 대한 크립키 논증의 의의와 한계를 비판적으로 다룸으로서 필자는 다음과 같은 점을 주장할 것이다. 비트겐슈타인에게 있어서 규칙은 우리들의 행동을 이끄는 지침의 역할을 하며, 규칙의 문제를 추론과 연관시켜 수학이 엄격한 규칙을 따르는 인간의 지적 활동이며, 규칙에 대한 비트겐슈타인의 관점은 귀납적 회의주의와 무관하다. 이런 맥락에서 비트겐슈타인을 회의주의자 혹은 상대주의자로 평가하는 것은 문제가 있다. 그런 점에서 비트겐슈타인은 오히려 어떤 이론이나 선입견에 사로잡히지 않은 봄의 방식을 강조한 철학자로 평가하는 것이 옳다.

• Transactions of the Korean Society of Mechanical Engineers A
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• v.28 no.5
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• pp.593-602
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• 2004

We have developed a digital control rod control system not only to improve its performance but also to improve its reliability and speed of response so that it can replace the old fashioned analog system. However, a new developed digital control system should be tested to prove the validity by using any prototype or mock-up before application. The reliability prediction and the reliability block diagram analysis methods were adopted to verify the reliability of the developed hardware. For the case of software, especially fur a new developed control algorithm it has been tested to prove performances and validation by using a dynamic simulator and mock-up of control rod drive mechanism altogether. Here we want to present some key factors regarding to the new developed digital system with some verification procedures.

• Proceedings of the Korean Information Science Society Conference
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• 2004.04b
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• pp.376-378
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• 2004

최근 클라이언트/서버 모델이 웹 기반의 컴퓨팅 환경으로 변화함에 딸라 웹 서비스 모델로 발전해왔다. 웹 서비스는 인터넷을 기반으로 표준화된 기술을 사용하여 서비스간에 상호작용을 함으로써. 플랫폼과 구현 언어에 대한 의존성을 제거 할 수 있다. 따라서, 다양한 환경에서 웹 서비스들이 개발되거나 개발 중에 있다. 기업에서는 표준화된 상호작용을 사용하여 작은 단위의 웹 서비스를 큰 단위의 렘 서비스로 통합하여 사용과 개발이 용이한 비즈니스 서비스를 제공하기 위한 통할 방법의 필요성이 증가하고 있다. 웹 서비스의 위상은 통합을 위한 메타 모델의 기능과 웹 서비스의 다양한 구현 형태로 이루어져 있다. 본 논문에서는 서비스 지향 아키텍처 상에서 공급자 측면에서 제공되는 웹 서비스를 통합하기 위한 위상을 제시하고자 한다. 이를 위해서, 웹 서비스를 논리적으로 계층화하여 정의하고, 논리적 계층 모델을 기반으로 웹 서비스 메타 모델을 생성한다. 위상의 다양한 구성은 메타 모델을 기반으로 제시된다. 마지막으로 웹 서비스 통합에 대한 사례연구를 제시한다.

• Journal of the Korean Institute of Telematics and Electronics C
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• v.36C no.10
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• pp.17-28
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• 1999

In this paper, an ASIC emulation system called ACE (ASIC Emulator) is proposed. It can produce the prototype of target ASIC in a short time and verify the function of ASIC circuit immediately The ACE is consist of emulation software in which there are EDIF reader, library translator, technology mapper, circuit partitioner and LDF generator and emulation hardware including emulation board and logic analyzer. Technology mapping is consist of three steps such as circuit partitioning and extraction of logic function, minimization of logic function and grouping of logic function. During those procedures, the number of basic logic blocks and maximum levels are minimized by making the output to be assigned in a same block sharing product-terms and input variables as much as possible. Circuit partitioner obtain chip-level netlists satisfying some constraints on routing structure of emulation board as well as the architecture of FPGA chip. A new partitioning algorithm whose objective function is the minimization of the number of interconnections among FPGA chips and among group of FPGA chips is proposed. The routing structure of emulation board take the advantage of complete graph and partial crossbar structure in order to minimize the interconnection delay between FPGA chips regardless of circuit size. logic analyzer display the waveform of probing signal on PC monitor that is designated by user. In order to evaluate the performance of the proposed emulation system, video Quad-splitter, one of the commercial ASIC, is implemented on the emulation board. Experimental results show that it is operated in the real time of 14.3MHz and functioned perfectly.

• Journal of The Korean Association For Science Education
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• v.18 no.4
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• pp.473-483
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• 1998

A learner's cognitive conflict with his /her existing conception is regarded to be one of the most important factors for a conceptual change. In this study, the effects of the conflict situation types on inducing students' cognitive conflicts in Newton's law were examined. The thirty-four students of 10th grade were selected from a rural high school based on the result of pre-test. The two different types of conflict situations among many possible types were used in this study. One type was using logical conflict situation and the other was demonstrating real conflict situation. The levels of cognitive conflict were measured by 4-point Likert scale by three interviewers. As the results, the demonstration method was more effective than the logical argument method. In case of the logical argument method, rather than showing scientific conceptions, suggesting another misconception was more effective to the students who have misconception. However, logical argument method was not effective to those who have scientfic conceptions. To the students who have unscientific conceptions, the demonstration method was very effective for inducing cognitive conflict. From the results of this study, demonstration method of teaching seems to be very effective for inducing students' cognitive conflict and overcoming their misconceptions on scientific concept.

• The Journal of the Institute of Internet, Broadcasting and Communication
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• v.9 no.1
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• pp.89-94
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• 2009

This paper proposes the algorithms that design the highly digital logic circuit and assign the code to each node of DCG(Directed Cyclic Graph) of length ${\zeta}$. The conventional algorithm have some problems, so this paper introduce the matrix equation from DCG of length ${\zeta}$ and proposes highly digital logic circuit design algorithms according to the DCG of length ${\zeta}$. Using the proposed circuit design algorithms in this paper, it become realized that was able to design from former algorithm. Also, making a comparison between the circuit using former algorithm and this paper's, we testify that proposed paper's algorithm is able to realize more optimized circuit design. According to proposed circuit design algorithm in this paper, it is possible to design current that DCG have natural number, so it have the following advantages, reduction of the circuit input/output digits, simplification of circuit composition, reduction of computation time and cost. And we show comparability and verification about this paper's algorithm.

• Journal of KIISE:Computer Systems and Theory
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• v.27 no.5
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• pp.529-539
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• 2000

This paper proposes a prefetch-based disk buffer management algorithm, which we call W2R (Veighingjwaiting Room). Instead of using elaborate prefetching schemes to decide which blockto prefetch and when, we simply follow the LRU-OBL (One Block Lookahead) approach and prefetchthe logical next block along with the block that is being referenced. The basic difference is that theW2R algorithm logically partitions the buffer into two rooms, namely, the Weighing Room and theWaiting Room. The referenced, hence fetched block is placed in the Weighing Room, while theprefetched logical next block is placed in the Waiting Room. By so doing, we alleviate some inherentdeficiencies of blindly prefetching the logical next block of a referenced block. Specifically, a prefetchedblock that is never used may replace a possibly valuable block and a prefetched block, thoughreferenced in the future, may replace a block that is used earlier than itself. We show through tracedriven simulation that for the workloads and the environments considered the W2R algorithm improvesthe hit rate by a maximum of 23.19 percentage points compared to the 2Q algorithm and a maximumof 10,25 percentage feints compared to the LRU-OBL algorithm.