• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.27 no.3
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• pp.317-325
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• 2016

This paper describes the technique for Radar Particle filter for TBD(Track Before Detect) processing. TBD technique is applied when target is difficult to detect due to low signal-to-noise ratio caused by strong clutter environments, small RCS targets and stealth targets. Particle filter is suitable for a recursive TBD algorithm and has improved estimation accuracy than Kalman filter. In this paper, we will present a new method of calculating particle weight, when observation values(including strong clutter) are received at the same time. Estimation error performance of the particle filter algorithm is analyzed by using the virtual radar observation scenario.

• Journal of Satellite, Information and Communications
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• v.10 no.2
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• pp.109-114
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• 2015

Frame synchronization is achieved by correlation between received symbols and a preamble pattern which is periodically appended at a frame header. In this paper, we deal with a frame detection method complaint with satellite-based DVB-S2 system. In DVB-S2, frame synchronization is performed under the low signal-to-noise ratio(SNR), a large frequency offset which can be up to 20% of a symbol transmission rate and unknown modulation schemes ranging from QPSK to 32-APSK. In this environment, we propose a method combining differential correlation based on SOF and PLSC with an accumulated correlation method for the detection of frame structures. In addition, detection performances about mean acquisition time(MAT) and detection error probability are evaluated via computer simulations.

• Journal of the Institute of Electronics Engineers of Korea TC
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• v.39 no.4
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• pp.173-179
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• 2002

This paper describes an equalizer using the DFE (Decision Feedback Equalizer) structure, CMA (Constant Modulus Algorithm) and LMS (Least Mean Square) algorithms. The DFE structure has better channel adaptive performance and lower BER than the transversal structure. The proposed equalizer can be used for 16/64 QAM modems. We employ high speed multipliers, square logics and many CSAs (Carry Save Adder) for high speed operations. We have developed floating-point models and fixed-point models using the COSSAP$\^$TM/ CAD tool and developed VHDL filter. The proposed equalizer shows low BER in multipath fading channel. We have performed models. From the simulation results, we employ a 12 tap feedback filter and a 8 tap feedforward logic synthesis using the SYNOPSYS$\^$TM/ CAD tool and the SAMSUNG 0.5$\mu\textrm{m}$ standard cell library (STD80) and verified function and timing simulations. The total number of gates is about 130,000.