• Title/Summary/Keyword: 기판접합

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A Study on the Channel Length and the Channel Punchthrough of Self-Aligned DMOS Transistor (자기정렬 DMOS 트랜지스터의 채널 길이와 채널 Punchthrough에 관한 고찰)

  • Kim, Jong-Oh;Kim, Jin-Hyoung;Choi, Jong-Su;Yoob, Han-Sub
    • Journal of the Korean Institute of Telematics and Electronics
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    • v.25 no.11
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    • pp.1286-1293
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    • 1988
  • A general closed form expression for the channel length of the self-aligned double-diffused MOS transistor is obtained from the 2-dimensional Gaussian doping profile. The proposed model in this paper is composed of the doping concentration of the substrate, the final surface doping concentration and the vertical junction depth of the each double-diffused region. The calculated channel length is in good agreement with the experimental results. Also, the optimum channel structure for the prevention of the channel puncthrough is obtained by the averaged doping concentration in the channel region. A correspondence between the results of device simulation of channel punchthrough and the estimations of simplified model is confirmed.

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A study on boron and phosphrous doping profile by RTA using 1MeV high energy ion implantaiton (1MeV 고에너지로 붕소(boron)와 인(phosphorus)을 이온주입 시급속 열처리에 따른 도핑 프로파일)

  • 강희원;전현성;노병규;조소행;김종규;김종순;오환술
    • Proceedings of the IEEK Conference
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    • 1998.06a
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    • pp.331-334
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    • 1998
  • p형 실리콘 기판위에 100.angs.의 초기 산화막을 성장시킨 후 붕소(B)와 인(P)을 1MeV 이온주입 에너지로 4.dec. tilting하여 붕소의 도즈량은 1*10/녀ㅔ 13/[cm/sup -2/]까지, 인은 1*10/sup 13/[cm/sup -2]로부터 1*10/sup 14/[cm/sup -2/] 까지 변화시키며 이온 주입하였다. 이온주입 후 RTA 로서 열처리 하였으며, 열처리 시간은 10초에서 40초까지,열처리 온도를 1000.deg.C에서 1100.deg.C까지 변화하였다. 이후 기파낸의 불순물의 프로파일 및 미세 결함의 분포를 분석하기 위하여, SIMS, SRP, XTEM 분석을 실시하였고, 이를 monte-carlo 모ㅓ델로서 시뮬레이션하여 비교하였다. SIMS 분석 결과 열처리 온도와 시간이 증가할수록 접합깊이가 증가하였고, 프로파일이 넓어짐을 볼수 있다. SRP 측정에서 붕소는 주해거리 (Rp)값은 1.8.mu.m~1.9.mu.m, 인의 경우는 1.1.mu.m~1.2.mu.m의 주행거리 (Rp) 값이 나타났다. XTEM 분석결과 붕소의 경우 열처리에 전후에도 결함을 볼수 없었고, 인의 경우 열처리 이후에 실리콘 결정내부에 있던 산소(O)와 인(P)우너자의 pinning효과에 의해 전위다이폴을 형성하여 표면근처로 성장함을 볼수 있었다.

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A Study on Pre-bonding of 3C-SiC Wafers using CVD Oxide (CVD 절연막을 이용한 3C-SiC 기판의 초기직접접합에 관한 연구)

  • ;;Shigehiro Nishino
    • Journal of the Korean Institute of Electrical and Electronic Material Engineers
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    • v.15 no.10
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    • pp.883-888
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    • 2002
  • SiC direct bonding technology is very attractive for both SiCOI(SiC-on-insulator) electric devices and SiC-MEMS(micro electro mechanical system) fields because of its application possibility in harsh environments. This paper presents pre-bonding techniques with variation of HF pre-treatment conditions for SiC wafer direct bonding using PECVD(plasma enhanced chemical vapor deposition) oxide. The PECYD oxide was characterized by XPS(X-ray photoelectron spectrometer) and AFM(atomic force microscopy). The characteristics of the bonded sample were measured under different bonding conditions of HF concentration and an applied pressure. The bonding strength was evaluated by the tensile strength method. The bonded interface was analyzed by using SEM(scanning electron microscope). Components existed in the interlayer were analyzed by using FT-IR(fourier transform infrared spectroscopy). The bonding strength was varied with HF pre-treatment conditions before the pre-bonding in the range of 5.3 kgf/cm$^2$to 15.5 kgf/cm$^2$.

An Experimental Investigation of LDD Device Optimization (LCD 소자 최적화의 실험적 고찰)

  • Kang, Dae-Gwan;Kim, Dal-Soo;Kim, Hyun-Chul;Song, Nag-Un
    • Journal of the Korean Institute of Telematics and Electronics
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    • v.27 no.3
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    • pp.72-78
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    • 1990
  • In this paper, the physical meanings of LDD optimization are treated by numerical simulation and related experiments are attempted to analyzed the optimized LDD structure. Firstly, according to the numerical analysis, the electric field under the n-region near drain is low and uniformly distributed and the current flow is widely distributed in this region under the optimized conditions. It is also found that this optimized point should be achieved by globally optimizing all the process and electrical conditions. Secondly, the maximum electric field, which is obtained from the substrate current to the drain current ratio, is minimized under the optimized condition according to the experiment. Further, the device lifetime is maximized and the n-resistance is changed smoothly from the channel resistance to the $n^+$junction resistance.

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Heat Transfer and Pressure Drop Characteristics in Zigzag Channel Angles of Printed Circuit Heat Exchangers (지그재그채널 PCHE의 각도에 따른 열전달 및 압력강하특성)

  • Choi, Mi-Jin;Kwon, Oh-Kyung;Cha, Dong-An;Yeun, Jae-Ho
    • Proceedings of the SAREK Conference
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    • 2009.06a
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    • pp.1147-1152
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    • 2009
  • The objectives of this paper are to study the characteristics of heat transfer and pressure drop of the zigzag channel PCHE using diffusion bonding technology by numerical analysis. PCHE of five types are designed, which are zigzag channel angle $180^{\circ}$, $160^{\circ}$, $140^{\circ}$, $120^{\circ}$ and $100^{\circ}$. The zigzag PCHE was numerically investigated for Reynolds number in a range of $150{\sim}800$. The temperatures of the hot side were performed at $80^{\circ}C$ while that of the cold side was conducted at $20^{\circ}C$. The results show that the performance of heat transfer rate for zigzag channel $100^{\circ}$ increases about 11.5% compared to that of zigzag channel $180^{\circ}$. On the other hand, the performance of pressure drop for zigzag channel $100^{\circ}$ is remarkably higher than that of zigzag channel $180^{\circ}$, about 1.4 times.

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A Study on the Copper Metallizing Method of $Al_2$O$_3$ Ceramic Surface (알루미나(Al$_2$O$_3$) 세라믹 표면의 강메탈라이징법에 관한 연구)

  • ;;Choi, Y. G.;Kim, Y. S.
    • Journal of Welding and Joining
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    • v.13 no.3
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    • pp.55-64
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    • 1995
  • Metallizing method on ceramic surface is one of the compositing technology of ceramics and metal. The purpose of this study is to make HIC (Hybrid Intergrated Circuit) with copper metallizing method of which copper layer is formed on ceramic substrate by firing in atmosphere in lieu of conventional hybrid microcircuit systems based on noble metal. Metallizing pastes were made from various copper compounds such as Cu$_{2}$O, CuO, Cu, CuS and kaolin. And the screen printing method was used. The characteristics of metallized copper layers were analyzed through the measurement of sheet resistance, SEM, and EDZX. The results obtainted are summarized as follows; 1. The copper metallizing layers on ceramic surface can be formed by firing in air. 2. The metallized layer using Cu$_{2}$O paste showed the smallest sheet resistance among a group of copper chemical compounds. And optimum metallizing conditions are 15 minutes of firing time, 1000.deg.C of firig temperature, and 3 minutes of deoxidation time. 3. The results of EDAX analysis showed mutual diffusion of Cu and Al. 4. The kaolin plays a important role of deepening the penetration of Cu to $Al_{2}$O$_{3}$ ceramics. But if the kaolin content is too much, sheet resistance increases and copper metallizing layer becomes brittle.

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YBCO step-edge junction dc SQUID magnetometers with multi-loop pickup coil fabricated on sapphire substrates (사파이어 기판을 사용한 병렬 검출코일 구조의 계단형 모서리 접합 SQUID 자력계)

  • 황태종;김인선;김동호;박용기
    • Progress in Superconductivity
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    • v.5 no.2
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    • pp.94-97
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    • 2004
  • Step-edge Josephson junctions (SEJ) have been fabricated on sapphire substrates with in situ deposited films of CeO$_2$ buffer layer and YBa$_2$Cu$_3$O$_{7}$ films on the low angle steps. Direct coupled SQUID magnetometers with the SEJ were formed on 1 cm X 1 cm R-plane sapphire substrates. Typical 5-${\mu}{\textrm}{m}$-wide Josephson junctions have R$_{N}$ of 3 Ω and I$_{c}$ of 50 $mutextrm{A}$ at 77 K. The direct coupled SQUID magnetometers were designed to have pickup coils of 50-${\mu}{\textrm}{m}$-wide 16 parallel loops on the 1 cm X 1 cm substrates with outer dimension of 8.8 mm X 8.8 mm. The SEJ SQUID magnetometers exhibit relatively low 1/f noise even with dc bias control, and could be stably controlled by flux-locked loops in the magnetically disturbed environment. Field noise of the do SQUID was measured to be 200∼300 fT/Hz$^{1}$2/in the white noise region and about 2 pT/Hz$^{1}$2/ at 1 Hz when measured with dc bias method.hod.d.

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InAs/GaAs 양자점 태양전지의 광학적 특성 평가: 접합계면전기장 및 AlGaAs 포텐셜 장벽효과

  • Kim, Jong-Su;Han, Im-Sik;Lee, Seung-Hyeon;Son, Chang-Won;Lee, Sang-Jo;Smith, Ryan P.;Ha, Jae-Du;Kim, Jin-Su;No, Sam-Gyu;Lee, Sang-Jun;Choe, Hyeon-Gwang;Im, Jae-Yeong
    • Proceedings of the Korean Vacuum Society Conference
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    • 2012.02a
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    • pp.107-107
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    • 2012
  • 본 연구에서는 GaAs p-i-n 태양전지구조에 InAs 양자점을 삽입하여 계면의 전기장 변화를 Photoreflectance (PR) 방법으로 연구하였다. InAs/GaAs 양자점 태양전지구조는 n-GaAs 기판위에 p-i-n 구조의 태양전지를 분자선박막성장 장치를 이용하여 제작하였다. GaAs p-i-n 태양전지와 p-QD(i)-n 양자점 태양전지를 제작하여 계면전기장의 변화를 PR 신호에 나타난 Franz-Keldysh oscillation (FKO)으로부터 측정하였다. 기본적인 p-i-n 구조에서 두 가지 전기장성분을 검출 하였고 양자점 태양전지구조에서는 39 kV/cm 이상의 내부전기장이 존재함을 관측하였다. 이러한 내부전기장은 양자점 주변에 형성된 국소전기장의 효과로 추측하였다. 아울러 양자점을 AlGaAs 양자우물 구조에 삽입하여 케리어의 구속에 의한 FKO의 변화를 관측하였으며 양자점 태양전지의 구조적 변화에 따른 효율을 측정하여 비교 분석하였다.

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Thermal Analysis on the Engineering Model of Command and Telemetry Unit for a Geostationary Communications Satellite (정지궤도 통신위성의 원격측정명령처리기 기술모델 열해석)

  • Kim, Jung-Hoon;Koo, Ja-Chun
    • Journal of the Korean Society for Aeronautical & Space Sciences
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    • v.32 no.9
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    • pp.114-121
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    • 2004
  • Thermal design changes and analysis on the engineering model of Command Telemetry Unit(CTU) for a geostationary communications satellite arc performed for the purpose of developing an engineering qualification model. A thermal model is developed by using power consumption measurement values of each functional board and thermal cycling test results. In modeling heat dissipated EEE parts, heat dissipation is imposed evenly on the EEE part footprint area which is projected to the printed circuit board. All the EEE parts of CTU meet the requirement of their allowable temperature range when placed on the engineering qualification level of thermal vacuum environments in accordance with the proposed thermal design changes.

Direct Bonding Characteristics of 2 inch 3C-SiC Wafers for MEMS in Hash Environments (극한환경 MEMS용 2 inch 3C-SiC 기판의 직접접합 특성)

  • Chung, Yun-Sik;Ryu, Ji-Goo;Kim, Kyu-Hyun;Chung, Gwiy-Sang
    • Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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    • 2002.11a
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    • pp.387-390
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    • 2002
  • SiC direct bonding technology is very attractive for both SiCOI(SiC-on-insulator) electric devices and SiC-MEMS(micro electro mechanical system) fields because of its application possibility in harsh environments. This paper presents pre-bonding techniques with variation of HF pre-treatment conditions for 2 inch SiC wafer direct bonding using PECVD(plasma enhanced chemical vapor deposition) oxide. The PECVD oxide was characterized by XPS(X-ray photoelectron spectrometer) and AFM(atomic force microscopy). The characteristics of the bonded sample were measured under different bonding conditions of HF concentration and an applied pressure. The bonding strength was evaluated by the tensile strength method. The bonded interface was analyzed by using IR camera and SEM(scanning electron microscope). Components existed in the interlayer were analyzed by using FT-IR(fourier transform infrared spectroscopy). The bonding strength was varied with HF pre-treatment conditions before the pre-bonding in the range of $5.3 kgf/cm^2$ to $15.5 kgf/cm^2$

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