• The Transactions of the Korean Institute of Power Electronics
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• v.25 no.3
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• pp.195-203
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• 2020

This paper presents a parasitic inductance reduction design method for the stable driving of GaN HEMT. To reduce the parasitic inductance, we propose a vertical lattice loop structure with multiple loops that is not affected by the GaN HEMT package. The proposed vertical lattice loop structure selects the reference loop and designs the same loop as the reference loop by layering. The design reverses the current direction of adjacent current paths, increasing magnetic flux cancellation to reduce parasitic inductance. In this study, we validate the effectiveness of the parasitic inductance reduction method of the proposed vertical lattice loop structure.

• Journal of IKEEE
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• v.23 no.3
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• pp.878-882
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• 2019

XOR(exclusive-OR)-XNOR(exclusive NOR) circuit is a basic component of 4-2 compressor for high performance arithmetic operation. In this paper we propose an energy efficient XOR-XNOR circuit. The proposed circuit is reduced the internal parasitic capacitance in critical path and implemented with 8 transistors. The circuit produces a perfect output signals for all input combinations. Compared with the previous circuits, the proposed circuit has a 14.5% reduction in propagation delay time and a 1.7% increase in power consumption. Therefore, the proposed XOR-XNOR is reduced power-delay- product (PDP) by 13.1% and energy-delay-product (EDP) by 26.0%. The proposed circuits are implemented with standard CMOS 0.18um technology and verified through SPICE simulation with 1.8V supply voltage.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.21 no.6
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• pp.591-600
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• 2010

In this paper, three kinds of 24 GHz low-power CMOS cross-coupled voltage controlled oscillators are designed and fabricated for a short-range radar applications using TSMC 0.13 ${\mu}m$ CMOS process. The basic CMOS crosscoupled voltage controlled oscillator is designed for oscillating around a center frequency of 24.1 GHz and subthreshold oscillators are developed for low power operation from it. A double resonant circuit is newly applied to the subthreshold oscillator to improve the problem that parasitic capacitance of large transistors in a subthreshold oscillator can push the oscillation frequency toward lower frequencies. The fabricated chips show the phase noise of -101~-103.5 dBc/Hz at 1 MHz offset, the output power of -11.85~-15.33 dBm and the frequency tuning range of 475~852 MHz. In terms of power consumption, the basic oscillator consumes 5.6 mW, while the subthreshold oscillator does 3.3 mW. The subthreshold oscillator with the double resonant circuit shows relatively lower power consumption and improved phase noise performance while maintaining a comparable frequency tuning range. The subthreshold oscillator with double resonances has FOM of -185.2 dBc based on 1 mW DC power reference, which is an about 3 dB improved result compared with the basic oscillator.

• Proceedings of the KIEE Conference
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• 2008.04c
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• pp.212-214
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• 2008

본 논문에서는 용량증대의 편리성, 유지 보수의 수월성, 전원에 따른 PCS 모듈화를 위해 연료전지와 같은 입력전원 증가 시 동일한 전력분배를 위한 PCS의 병렬운전기법이 적용된 연료전지 발전시스템을 개발하였다. 또한 다중 연료전지 발전시스템 PCS의 기생 성분의 영향을 분석하고 시뮬레이션 및 실험을 통해 검증하였다.

• The Proceedings of the Korean Institute of Illuminating and Electrical Installation Engineers
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• v.10 no.6
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• pp.54-61
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• 1996

In this paper, the conventional ZVS-QRC buck dc-dc converter is analyzed using simulation and the problem in confirmed through it. According to varying the load resistance lower, it is provided that the stress of the device is increased. The reason is seen that the voltage is increased by parasitic capacitance of freewheeling diode. Novel ZVS-converter is proposed to improve the problems.

• Proceedings of the KIEE Conference
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• 2000.07d
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• pp.3142-3144
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• 2000

청각시스템의 저전력 및 가격의 저렴화를 위해 달팽이관의 BM(Basilar Membrain)모델을 아날로그 VLSI 마이크로 파워 공정으로 구현하고 있다. Lyon and Mead는 실리론 공정으로 달팽이관 모델을 효과적으로 구현하였다. 이는 단순 직렬 연결된 구조로 각 채널의 지연시간의 차이로 인해 인식율이 떨어질 수 있다. 본 논문에서는 소리의 주파수 정보 추출기능을 하는 직렬 연결된 트리구조(TSBF:Tree-structured Cascaded Bandpass Filter)의 16채널의 아날로그 중간대역통과 필터회로를 CMOS VLSI 공정을 이용하여 설계하였다. 직렬 연결된 저대역통과필터와 고대역통과필터로 각 채널의 중간대역통과 필터를 구현하였다. 이러한 구조에서는 각 채널의 지연시간이 동일하므로 인식율을 높일 수 있다. 그리고 고대역통과필터를 1-poly 디지털 공정으로 구현 가능하고 기생 캐패시터의 영향을 적게 받는 구조로 설계하였다.

• Proceedings of the KIEE Conference
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• 2005.10c
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• pp.205-207
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• 2005

플라이백 컨버터의 경계점 도통 모드 운전은 변압기의 자화인덕턴스 전류를 연속과 불연속의 경계에서 도통시킴으로써 기존의 고정주파수 컨버터에서 소프트 스위칭을 위하여 사용하였던 별도의 스위치나 보조회로를 추가하지 않으면서 전력소자의 소프트 스위칭을 가능하게 하는 장점을 가진다. 본 논문에서는 스위치의 온 오프시 변압기의 인덕턴스와 스위치의 기생 커패시터 성분이 일으키는 공진구간을 전체 스위칭 주기에 포함시킴으로써 경계점 도통 모드 운전에서 부하출력에 따른 스위칭 주파수의 변화를 보다 정확히 제시하고 이를 바탕으로한 정상상태모델링을 통하여 경계점 도통 모드 플라이백 컨버터의 여러 운전 특성을 분석하였다.

• Journal of the Institute of Electronics and Information Engineers
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• v.54 no.1
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• pp.33-38
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• 2017

In this paper, a 4-channel common-cathode VCSEL diode driver array with 3.125 Gb/s per channel operation speed is realized. In order to achieve faster speed of the switching main driver with relatively large transistors, the transmitter array chip consists of a pre-amplifier with active inductor stage and also an input buffer with modified equalizer, which leads to bandwidth extension and reduced current consumption. The utilized VCSEL diode provides inherently 2.2 V forward bias voltage, $50{\Omega}$ resistance, and 850 fF capacitance. In addition, the main driver based upon current steering technique is designed, so that two individual current sources can provide bias currents of 3.0 mA and modulation currents of 3.3 mA to VCSEL diodes. The proposed 4-channel VCSEL driver array has been implemented by using a $0.11-{\mu}m$ CMOS technology, and the chip core occupies the area of $0.15{\times}0.18{\mu}m^2$ and dissipates 22.3 mW per channel.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.47 no.3
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• pp.18-27
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• 2010

In this paper, a 1.2V 7-bit 1GSPS A/D converter with offset self-calibration is proposed. The proposed A/D converter structure is based on the folding-interpolation whose folding rate is 2, interpolation rate is 8. Further, for the purpose of improving the chip performance, an offset self-calibration circuit is used. The offset self-calibration circuit reduce the variation of the offset-voltage，due to process mismatch, parasitic resistor, and parasitic capacitance. The chip has been fabricated with a 1.2V 65nm 1-poly 6-metal CMOS technology. The effective chip area is $0.87mm^2$ and the power dissipates about 110mW at 1.2V power supply. The measured SNDR is about 39.1dB when the input frequency is 250MHz at 800MHz sampling frequency. The measured SNDR is 3dB higher than the same circuit without any calibration.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.23 no.10
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• pp.1137-1144
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• 2012

In this paper, a 2.6 GHz switched parasitic array(SPA) antenna is designed to resolve the device interference in the femtocell. The designed SPA antenna structure consists of a central ${\lambda}/4$ monopole antenna as a radiator and surrounding four parasitic elements operating as a reflector or a director depending on the switching state. In addition, open state monopoles around the parasitic elements are placed to improve the directivity. The designed antenna utilizes RF FETs as switching elements instead of conventional PIN diodes, which enables beam steering with a simple structure consuming low power. To select the proper FET switch, the performance of the SPA antenna depending on the switch characteristics is analyzed. The fabricated antenna has 65 mm radius and 35 mm height, which shows about 15 dB front-back-ratio(FBR) at 2.6 GHz and enables eight-directional beam steering.