• Journal of Educational Research in Mathematics
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• v.27 no.4
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• pp.833-855
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• 2017

This study aims to reinvestigate the reason for introducing radian as a new unit to express the size of angles, what is the meaning of radian measures to use arc lengths as angle measures, and why is the domain of trigonometric functions expanded to real numbers for expressing general angles. For this purpose, it was conducted historical, mathematical and applied mathematical analyzes in order to research at multidisciplinary analysis of the radian concept. As a result, the following were revealed. First, radian measure is intrinsic essence in angle measure. The radian is itself, and theoretical absolute unit. The radian makes trigonometric functions as real functions. Second, radians should be aware of invariance through covariance of ratios and proportions in concentric circles. The orthogonality between cosine and sine gives a crucial inevitability to the radian. It should be aware that radian is the simplest standards for measuring the length of arcs by the length of radius. It can find the connection with sexadecimal method using the division strategy. Third, I revealed the necessity by distinction between angle and angle measure. It needs justification for omission of radians and multiplication relationship strategy between arc and radius. The didactical suggestions derived by these can reveal the usefulness and value of the radian concept and can contribute to the substantive teaching of radian measure.

• Journal of Elementary Mathematics Education in Korea
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• v.20 no.1
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• pp.105-129
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• 2016

The elements of mathematical processes include mathematical reasoning, mathematical problem-solving, and mathematical communications. Proportion reasoning is a kind of mathematical reasoning which is closely related to the ratio and percent concepts. Proportion reasoning is the essence of primary mathematics, and a basic mathematical concept required for the following more-complicated concepts. Therefore, the study aims to analyze the proportion reasoning ability of sixth graders of primary school who have already learned the ratio and percent concepts. To allow teachers to quickly recognize and help students who have difficulty solving a proportion reasoning problem, this study analyzed the characteristics and patterns of proportion reasoning of sixth graders of primary school. The purpose of this study is to provide implications for learning and teaching of future proportion reasoning of higher levels. In order to solve these study tasks, proportion reasoning problems were developed, and a total of 22 sixth graders of primary school were asked to solve these questions for a total of twice, once before and after they learned the ratio and percent concepts included in the 2009 revised mathematical curricula. Students' strategies and levels of proportional reasoning were analyzed by setting up the four different sections and classifying and analyzing the patterns of correct and wrong answers to the questions of each section. The results are followings; First, the 6th graders of primary school were able to utilize various proportion reasoning strategies depending on the conditions and patterns of mathematical assignments given to them. Second, most of the sixth graders of primary school remained at three levels of multiplicative reasoning. The most frequently adopted strategies by these sixth graders were the fraction strategy, the between-comparison strategy, and the within-comparison strategy. Third, the sixth graders of primary school often showed difficulty doing relative comparison. Fourth, the sixth graders of primary school placed the greatest concentration on the numbers given in the mathematical questions.

• The Journal of the Acoustical Society of Korea
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• v.23 no.8
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• pp.554-561
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• 2004

As the technologies of semiconductor and multimedia communication have been improved. the high-quality video and the multi-channel audio have been highlighted. MPEG Audio Layer 3 decoder has been implemented as a Processor using a standard. Since the synthesis filter of MPEG-1 Audio Layer 3 decoder requires the most outstanding operation in the entire decoder. the synthesis filter that can reduce the amount of operation is needed for the design of the high-speed processor. Therefore, in this paper, the synthesis filter. the most important part of MPEG Audio, is materialized in FPGA using the method of DAULT (distributed arithemetic look-up table). For the design of high-speed synthesis filter, the DAULT method is used instead of a multiplier and a Pipeline structure is used. The Performance improvement by 30% is obtained by additionally making the result of multiplication of data with cosine function into the table. All hardware design of this Paper are described using VHDL (VHIC Hardware Description Language) Active-HDL 6.1 of ALDEC is used for VHDL simulation and Synplify Pro 7.2V is used for Model-sim and synthesis. The corresponding library is materialized by XC4013E and XC4020EX. XC4052XL of XILINX and XACT M1.4 is used for P&R tool. The materialized processor operates from 20MHz to 70MHz.

• The KIPS Transactions:PartA
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• v.12A no.5 s.95
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• pp.451-460
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• 2005

We present a methodology to design energy-efficient data paths using FPGAs. Our methodology integrates domain specific modeling, coarse-grained performance evaluation, design space exploration, and low-level simulation to understand the tradeoffs between energy, latency, and area. The domain specific modeling technique defines a high-level model by identifying various components and parameters specific to a domain that affect the system-wide energy dissipation. A domain is a family of architectures and corresponding algorithms for a given application kernel. The high-level model also consists of functions for estimating energy, latency, and area that facilitate tradeoff analysis. Design space exploration(DSE) analyzes the design space defined by the domain and selects a set of designs. Low-level simulations are used for accurate performance estimation for the designs selected by the DSE and also for final design selection We illustrate our methodology using a family of architectures and algorithms for matrix multiplication. The designs identified by our methodology demonstrate tradeoffs among energy, latency, and area. We compare our designs with a vendor specified matrix multiplication kernel to demonstrate the effectiveness of our methodology. To illustrate the effectiveness of our methodology, we used average power density(E/AT), energy/(area x latency), as themetric for comparison. For various problem sizes, designs obtained using our methodology are on average $25\%$ superior with respect to the E/AT performance metric, compared with the state-of-the-art designs by Xilinx. We also discuss the implementation of our methodology using the MILAN framework.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.27 no.2
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• pp.170-175
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• 2016

In order to transmit baseband signals through frequency dividing devices, we studied the transfer function of the device in the term of the baseband signal distortion. From the analysis, it is shown that the magnitude of the envelope signal is related to the mixer gain and the insertion loss of the low pass filter whilst the phase is the additional function with the 1/2 of the phase delay. For the purpose of the verification of the study, we designed a dynamic frequency divider at 1,400 MHz. The operating frequency range of the device is closely related to the conversion gain of mixers and the amplitude of input signal, and becomes wide as the conversion gain of mixers increases. The designed frequency divider operates between 0.9 GHz and 3.2 GHz, for -14.5 dBm input power. The circuit shows 20 mW power dissipation at $V_{DD}=2.5V$, and the simulation result shows that an amplitude modulated signal at 1,400 MHz with the modulation index of 0.9 was successfully downconverted to 700 MHz.

• Journal of the Institute of Electronics Engineers of Korea SP
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• v.42 no.1
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• pp.87-94
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• 2005

In this paper a low-power DWT(Discrete Wavelet Transform) design technique is proposed. As basic low-pass filter for analysis bank, comb filter is utilized, and in order to improve frequency response for the comb filter, a fourth order polynomial is also proposed. Another filters are designed by using perfect reconstruction conditions. The lowpass filter coefficients of the analysis filter bank are optimized based on the cost function and perfect reconstruction condition. The number of the multiplications and MSE(Mean Squared Error) performance of the proposed DWT filter bank are compared with those of the JPEG2000 (9, 7) filter bank. It is shown that number of multiplications of the proposed filter bank are saved with 33.3%, and MSE values of the proposed filter bank are also superior to those of the JPEG2000 (9, 7) filter bank.

• Journal of the Institute of Electronics and Information Engineers
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• v.51 no.6
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• pp.34-42
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• 2014

This paper presents a low-complexity and high-throughput symbol detector for two-spatial-stream multiple-input multiple-output systems based on the modified maximum-likelihood symbol detection algorithm. In the proposed symbol detector, the cost function is calculated incrementally employing a multi-cycle architecture so as to eliminate the complex multiplications for each symbol, and the slicing operations are performed hierarchically according to the range of constellation points by a pipelined architecture. The proposed architecture exhibits low hardware complexity while supporting complicated modulations such as 256 QAM. In addition, various modulations and antenna configurations are supported flexibly by reconfiguring the pipeline for the slicing operation. The proposed symbol detector is implemented with 38.7K logic gates in a $0.11-{\mu}m$ CMOS process and its throughput is 166 Mbps for $2{\times}$3 16-QAM and 80Mbps for $2{\times}3$ 64-QAM where the operating frequency is 478 MHz.

• Journal of the Institute of Electronics Engineers of Korea SP
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• v.47 no.1
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• pp.139-149
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• 2010

Random scalar countermeasures, which carry out the scalar multiplication by the ephemeral secret key, against the differential power analysis of ECIES and ECDH have been known to be secure against various power analyses. However, if an attacker can find this ephemeral key from the one power signal, these countermeasures can be analyzed. In this paper, we propose a new power attack method which can do this analysis. Proposed attack method can be accomplished while an attacker compares the elliptic curve doubling operations and we use the principle component analysis in order to ease this comparison. When we have actually carried out the proposed power analysis, we can perfectly eliminate the error of existing function for the comparison and find a private key from this elimination of the error.

• Journal of the Institute of Electronics Engineers of Korea CI
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• v.43 no.2 s.308
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• pp.52-62
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• 2006

In a fuzzy control system to process fuzzy data in high-speed for intelligent systems, one of the important problems is the improvement of the execution speed in the fuzzy inference and defuzzification stages. Especially, it is more important to have high-speed operations in the consequent part and defuzzification stage. Therefore, in this paper, to improve the speedup of the fuzzy controllers for intelligent systems, we propose an integer line mapping algorithm using only integer addition to convert [0,1] real values in the fuzzy membership functions in the consequent part to integer grid pixels $(400{\times}30)$. This paper also shows a novel defuzzification algorithm without multiplications. Also we apply the proposed system to the truck backer-upper control system. As a result, this system shows a real-time very high speed fuzzy control as compared as the conventional methods. This system will be applied to the real-time high-speed intelligent systems such as robot arm control.

• Journal of the Korea Society of Computer and Information
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• v.18 no.8
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• pp.87-93
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• 2013

A baby-step giant-step algorithm divides n by n blocks that possess $m={\lceil}\sqrt{n}{\rceil}$ elements, and subsequently computes and stores $a^x$ (mod n) for m elements in the 1st block. It then calculates mod n for m blocks and identifies each of them with those in the 1st block of an identical elemental value. This paper firstly proposes a modified baby-step giant-step algorithm that divides ${\lceil}m/2{\rceil}$ blocks with m elements applying $a^{{\phi}(n)/2}{\equiv}1(mod\;n)$ and $a^x(mod\;n){\equiv}a^{{\phi}(n)+x}$ (mod n) principles. This results in a 50% decrease in the process of the giant-step. It then suggests a reverse baby-step giant step algorithm that performs and saves ${\lceil}m/2{\rceil}$ blocks firstly and computes $a^x$ (mod n) for m elements. The proposed algorithm is found to successfully halve the memory and search time of the baby-step giant step algorithm.