• Journal of the Korea Institute of Information and Communication Engineering
• /
• v.25 no.6
• /
• pp.813-818
• /
• 2021

This paper proposes an optimized hardware implementation method for existing CIE1931 color gamut control algorithm. Among the post-processing methods of dehazing algorithms, existing algorithm with relatively low computations have the disadvantage of consuming many hardware resources by calculating large bits using Split multiplier in the computation process. The proposed algorithm achieves computational reduction and hardware miniaturization by reducing the predefined two matrix multiplication operations of the existing algorithm to one. And by optimizing the Split multiplier computation, it is implemented more efficient hardware to mount. The hardware was designed in the Verilog HDL language, and the results of logical synthesis using the Xilinx Vivado program were compared to verify real-time processing performance in 4K environments. Furthermore, this paper verifies the performance of the proposed hardware with mounting results on two FPGAs.

• 한국공간정보시스템학회:학술대회논문집
• /
• 2007.06a
• /
• pp.111-116
• /
• 2007

현재 한강수계를 제외한 3대강 수계에서 수질오염총량관리제도가 의무제로써 시행되고 있다. 그러나 과학적 타당성과 외국의 성공사례들로 하여금 한강수계에 대해서도 수질오염총량제도를 의무제화 하려는 시도가 추진되고 있고 있는 실정이다. 이 제도가 한강수계에도 도입된다면, 한강권역에 포함되는 모든 지자체는 해당 유역에서 하천으로 유입되는 배출부하량을 할당받은 할당부하량 이하로 관리하여야만 정해진 유역의 목표수질을 달성할 수 있으며, 배출부하량 관리를 계획한데로 이행하지 못한 지자체는 범칙금 내지는 행정제재를 받게 된다. 따라서 체계적이고 과학적인 모니터링 및 분석 수단이 필요하다. 이 연구는 환경부 고시 한강기술지침에 의거하여 GIS를 이용하여 인천일대의 오폐수 발생부하량 및 배출부하량을 제시하고 과학적인 오염물질 삭감방안을 모색하는 것을 목적으로 진행되었다. 생활계, 산업계, 축산계, 양식계의 4 가지로 분류된 점오염원과 토지 이용 분류에 따른 비점오염원에 대한 각각의 발생부하량을 GIS를 통해 산정하고, 모든 오염원별로 처리경로를 고려하고 처리시설별, 방법별 삭감 효율을 반영하여 배출부하량을 산정하여 GIS상에서 제시하고 분석하였다. 인천일대는 인근지역에 비해 인구밀도가 높고 산업단지가 발달하여 생활계와 산업계 오염원에 의한 발생부하량 및 배출부하량이 많았으며, 특정 오염물에 대해서는 삭감 계획이 필요함을 확인할 수 있었다. 따라서 수질오염총량관리제도에 대비하고 실제 수질 개선을 위하여 본 연구의 결과를 바탕으로 수질관리를 위한 시스템의 보완 및 삭감계획의 수립에 관한 연구가 필요하다.알 수 있었다. 이상의 결과를 토대로 기존 압출추출방법과 초임계 추출 방법을 비교한 결과 $\gamma$-토코페롤의 농도가 1.3${\~}$1.6배 증가함을 확인할 수 있었다.게 상관성이 있어 앞으로 심도 있는 연구가 더욱 필요하다.qrt{F}}}{\pm}e_0$)에서 단정도실수 및 배정도실수의 역수 제곱근 계산에 필요한 평균 곱셈 횟수를 계산한다 이들 평균 곱셈 횟수를 종래 알고리즘과 비교하여 본 논문에서 제안한 알고리즘의 우수성을 증명한다. 본 논문에서 제안한 알고리즘은 오차가 일정한 값보다 작아질 때까지만 반복하므로 역수 제곱근 계산기의 성능을 높일 수 있다. 또한 최적의 근사 역수 제곱근 테이블을 구성할 수 있다. 본 논문의 연구 결과는 디지털 신호처리, 컴퓨터 그라픽스, 멀티미디어, 과학 기술 연산 등 부동소수점 계산기가 사용되는 분야에서 폭 넓게 사용될 수 있다.>16$\%$>0$\%$ 순으로 좋게 평가되었다. 결론적으로 감농축액의 첨가는 당과 탄닌성분을 함유함으로써 인절미의 노화를 지연시키고 저장성을 높이는데 효과가 있는 것으로 생각된다. 또한 인절미를 제조할 때 찹쌀가루에 8$\%$의 감농축액을 첨가하는 것이 감인절미의 색, 향, 단맛, 씹힘성이 적당하고 쓴맛과 떫은맛은 약하게 느끼면서 촉촉한 정도와 부드러운 정도는 강하게 느낄수 있어서 전반적인 기호도에서 가장 적절한 방법으로 사료된다.비위생 점수가 유의적으로 높은 점수를 나타내었다. 조리종사자의 위생지식 점수와 위생관리

• Journal of the Institute of Electronics Engineers of Korea SD
• /
• v.46 no.1
• /
• pp.59-67
• /
• 2009

In this paper, we have proposed the structure of the IMADF(improved modified multiplication-free adaptive filter) to cancel the adaptive noise in biomedical signals. The IMADF structure use the one-step predicted filter in the multiplication-free adaptive digital filter(MADF) structure using the DPCM and Sign algorithm. And then we use the heart phantom model based on the magnetocardiographic (MCG) to test the biomedical signals and analyze the signal of it. Their functions of the heart phantom occur from the multidipole current source. This can play role the same in the real function of the human heart to study it. In the experimental results, the IMADF algorithm has reduced the computational complexity by use of only the addition operation without a multiplier. Also, under the condition of identical stationary-state error, it could obtain the stabled convergence characteristics that the IMADF algorithm is almost same as the sign algorithm, but is better than the MADF algorithm. Here, this algorithm has effective characteristics when the correlation of the input signal is highly.

• Journal of the Korea Society of Computer and Information
• /
• v.18 no.8
• /
• pp.87-93
• /
• 2013

A baby-step giant-step algorithm divides n by n blocks that possess $m={\lceil}\sqrt{n}{\rceil}$ elements, and subsequently computes and stores $a^x$ (mod n) for m elements in the 1st block. It then calculates mod n for m blocks and identifies each of them with those in the 1st block of an identical elemental value. This paper firstly proposes a modified baby-step giant-step algorithm that divides ${\lceil}m/2{\rceil}$ blocks with m elements applying $a^{{\phi}(n)/2}{\equiv}1(mod\;n)$ and $a^x(mod\;n){\equiv}a^{{\phi}(n)+x}$ (mod n) principles. This results in a 50% decrease in the process of the giant-step. It then suggests a reverse baby-step giant step algorithm that performs and saves ${\lceil}m/2{\rceil}$ blocks firstly and computes $a^x$ (mod n) for m elements. The proposed algorithm is found to successfully halve the memory and search time of the baby-step giant step algorithm.

• The Transactions of the Korea Information Processing Society
• /
• v.1 no.2
• /
• pp.237-243
• /
• 1994

Fast curve generation is one of important techniques which facilitate fast process of computer graphics applications. It is possible to resolve the task through hardware or software. But rapid development of computer graphics area need methods for more fast generation of curves. This paper propose a algorithm (called CDAUD), which computes the coordinates of points on curve only with add operations using for ward differences and draw the curve fast. It also contains the method for generation of smooth and fully connected curves. Time complexity of CDAUD shows that it is superior than the existing method for constrained case, and it's superiority was validated through experimental implementation.

• Journal of the Korean Institute of Telematics and Electronics T
• /
• v.36T no.1
• /
• pp.1-7
• /
• 1999

We present VLSI architecture for a high performance 2-D DCT processor which is used compressing system of real time image processing or HDTV using fast computational algorithm of the Optimized Integer Cosine Transform(OICT). The coefficients of the OICT are integer, so the OICT performs only the integer operations for both forward and inverse transform. Therefore the proposed architecture could be greatly enhanced in improving the speed, reduced the hardware cost considerably by replacing the multiplication operations with shift and addition operations compared with DCT which performs floating-point operations.

• Journal of KIISE:Computer Systems and Theory
• /
• v.28 no.10
• /
• pp.520-529
• /
• 2001

Carry-save-adder(CSA) is one of the most effective operation cells in implementing an arithmetic hardware with high performace and small circuit area. An fundamental drawback of the existing CAS applications is that the applications are limited to the local parts of arithmetic circuit that are directly converted to additions. To resolve the limitation, we propose a set of new CSA transformation techniques: optimizing arithmetics with multiplexors, optimizing arithmetics in multiple designs, and optimizing arithmetics with multiplications. We then design a new CSA transformation algorithm which integrates the proposed techniques, so that we are able to utilize CSAs more globally. An extensive experimentation for practical designs are provided to show the effectiveness of our proposed algorithm over the conventional CSA techniques.

• Journal of Korea Multimedia Society
• /
• v.6 no.3
• /
• pp.549-555
• /
• 2003

CA is cost-effective to generate pseudorandom patterns than LFSR. Based on the effectiveness of a CA based pseudorandom pattern generator, CA have been employed successfully in several applications. Especially Nongroup CA is applied to efficient hash function generation, cryptography and image compression. In this paper we analyze the properties of TPNCA and by using basic paths in the 0-tree of a linear TPNCA we analyze the structure of the state-transition graph. Also by showing the structure of the complemented CA which have the acyclic state of the 0-tree as the complement vector is isomorphic to the structure of the original TPNCA, we reduce the time in analyzing the CA-states.

• The Journal of Korean Institute of Communications and Information Sciences
• /
• v.19 no.4
• /
• pp.685-690
• /
• 1994

A problem associated with vector quantization(VQ) is the computational complexity incurred in searching for a codevector with the closet to a given input vector, where the complexity increases exponentionally with proportion to codebook size and then limits practical application. In this paper, a simple and fast, but efficient, VQ encoding algorithm is presented using a reference codevector as start codevector of premature exit condition, which eliminates distance claculation of unlikely codevectors. The algorithm is to find reference codevector having the possibility to be the nearest vector to input vector first and then to incorporate premature exit condition. The proposed algorithm needs only 10~15% of mathematical operations compared with the conventional full search VQ. Algorithm the number of additions and comparsions of the proposed algorithm is not reduced greatly, the number of multiplication is reduced up to 70~80% compared with other fast VQ encoding methods.

• The Journal of Korean Institute of Communications and Information Sciences
• /
• v.29 no.1C
• /
• pp.35-44
• /
• 2004

In this paper, we design an efficient VLSI architecture of entropy coding algorithm in JPEG2000. Entropy coder is a context-based binary arithmetic encoder, and composed of a Context Extractor(CE) and an Arithmetic Coder(AC). We speed-up CE by skipping no-operation bits in coding passes, and AC is to be performed based on MQ coder. Because of using Qe value associated with each allowed context and probability estimation, MQ coder is a multiplication free coder that reduces computation loads and makes simple the structure of arithmetic coder. We have developed and synthesized the VHDL models of CE and AC pairs using Xilinx FPGA technology. The proposed architecture operates up to 30MHz.