• Proceedings of the KIPE Conference
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• 2020.08a
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• pp.245-247
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• 2020

본 논문에서는 DUT(Device Under Test) 및 PHIL(Power Hardware-in-the-Loop) 시뮬레이터의 스위칭 주파수 비 및 PWM 위상차에 의하여 발생할 수 있는 문제를 분석하였다. 또한, DUT 인버터의 PWM 특성을 고려한 디지털 필터를 적용하여 PHIL 시뮬레이터의 운전 영역을 확대하였다. 디지털 필터는 DUT 스위칭 주파수의 고조파 성분만을 선택적으로 제거하여 PHIL 스위칭 주파수에 무관하게 일정한 시뮬레이션 결과를 생성할 수 있다. 분석한 내용과 디지털 필터의 변경으로 인한 PHIL 시뮬레이터의 특성은 다양한 조건에서 시행된 실험을 통하여 검증하였다.

• Journal of the Korean Institute of Telematics and Electronics T
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• v.35T no.3
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• pp.37-45
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• 1998

In this paper, the different frequency component and time informations from an EMI signal are extracted simultaneously using a wavelet transform and the results of transform in the time and frequency domain are analyzed. Frequencies are extracted from the EMI signal by performing the multiresolution analysis using the Daubechies-4 filter coefficients and the time information through the results of wavelet transform. We have tried the correlation analysis to evaluate the results of wavelet transform. We have chosen the optimal wavelet function for an object signal by comparing the transformed results of various wavelet functions and verified the simulation examples of waveform and harmonic analysis using a wavelet transform. We have proved the denoising effect to the EMI signal using the soft thresholding technique.

• Proceedings of the KIEE Conference
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• 1998.07f
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• pp.1960-1962
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• 1998

Reference/modulating waveform continuity is not a necessary condition for the implementation of switching patterns for three-phase pulse-width modulated(PWM) converters. This is based on the fact that the converter phase-voltages do not need to be sinusoidal and switching pattern discontinuities do not degrade the quality of output/input voltage/current waveforms by introducing low-order harmonics if certain parameters are optimized. This paper introduces the selected harmonic elimination to reduce the switching frequency and low-order harmonics compared with continuous PWM techniques and some discontinues switching patterns for PWM converter.

• The Transactions of the Korean Institute of Power Electronics
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• v.4 no.4
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• pp.342-348
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• 1999

This paper describes a low-cost single-phase active power filter, which consists of a half-bridge P\A미1 inverter with a s simple control circuit. In order to verify the performance of proposed active power filter, many computer simulations w with EMTP codes and experimental works with a hardware prototype were done. Both results confirm that the p proposed active power filter shows excellent performance to eliminate the harmonics generated in the single-phase non l linear‘ load. The active power filter has advantage of low implementation cost and compact size. using a half-bridge i inverter and a simple control circuit with only one current sensor. So. it can be fabricated as a plug-in type.

• Journal of the Institute of Electronics Engineers of Korea TC
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• v.44 no.2
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• pp.81-86
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• 2007

In this paper, the Power Added Efficiency (PAE) and linearity of class-F PA has been improved by using the PBG structure and the application of EER structure, simultaneously. The adaptive bias control circuit has been employed to improve the PAE through the application of EER structure. The PBG structure has been adapted for improving the Linearity by suppressing the harmonics on the output of amplifier. The PAE and the 3rd Inter-Modulation Distortion (IMD) has improved 34.56%, 10.66 dB, compared with those of the conventional Doherty amplifier, respectively.

• Proceedings of the KIEE Conference
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• 2006.07a
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• pp.220-221
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• 2006

This paper presents a single-phase parallel active power filter with an analog control circuit to eliminate for harmonic source currents generated by nonlinear loads. The proposed system removes the harmonic source currents by injecting a compensation current that is 180' out of phase with the load harmonic current. The detection of the load harmonics is realized by a simple new structure, referred to the Notch Filter with GIC (Generalized Impedance Converter), which has higher Q than existing harmonic detecters and a simpler structure. The compensation current is obtained using the proposed harmonic detection circuit, DC-Link voltage, and output current of the full-bridge inverter controlled current mode PWM controller. The operation of the proposed system is verified experimentally.

• Proceedings of the KIEE Conference
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• 1989.11a
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• pp.296-300
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• 1989

The paper proposes a method to eliminate harmonics of PWM inverter fed induction motor system using Walsh series. In other words, this paper presents technique of the selective harmonics elimination(SHE) by W-FT series in three phase PWM inverter output waveform. A microprocessor(8086 CPU) - controlled three phase induction motor system in order to verify this algorithm is present. It is designed for a three output voltage in the 1$\sim$60 Hz inverter with the 5th and 7th harmonics, 5th, 7th, 11th, and 13th, harmonics eliminated, and with the fundamental wave amplitude proportional to the output frequency. In the PWM inverter, dead time circuit is inserted in the switching si gnats to prevent the de link shortage. This paper is deals with quantative prediction of dead-time effect and its compensation in PWM inverters. The performance of the compensation circuits is confirmed by the experiment.

• Journal of the Institute of Electronics Engineers of Korea TC
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• v.47 no.2
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• pp.80-85
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• 2010

In this paper, the efficiency of power amplifier has been maximized by the application of EER structure, and the linearity has been improved by using metamaterial structure. This paper has proposed a design of power amplifier in class-F to get the PAE, and to control dynamic power using envelope detector. CRLH structure gets high-linearity by removing harmonics arisen from the mismatching of matching circuit. The PAE and the 3rd order IMD have been improved 5.93 %, 12.83 dB compared with those of conventional Class-F amplifier, respectively.

• The Journal of The Korea Institute of Intelligent Transport Systems
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• v.8 no.1
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• pp.45-52
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• 2009

In this paper, a new rectenna is presented for the wireless transmission of microwave power using dipole antenna (Quasi Yagi effect) and rectifier of CPS resonator structure. The dipole antenna with CPW feedline has high peak gain than a general dipole antenna. A ground plane of CPW is used to reflect a dipole as a Yagi antenna. Therefore, the new rectenna receives the RF power better than the one using general dipole. A RF-to-DC conversion efficiency of 61 % using a 1.4 $k{\Omega}$ load resistor is obtained at 5.8 GHz.

• 한국초전도학회:학술대회논문집
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• v.10
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• pp.193-196
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• 2000

A new type low-pass filter design method based on a coupled line and transmission line theory is proposed to suppress harmonics by attenuation poles in the stop band. The design formula are derived using the equivalent circuit of a coupled transmission line. The new low-pass filter structure is shown to have attractive properties such as compact size, wide stop band range and low insertion loss. The seventh-order low-pass filter designed by present method has a cutoff frequency of 0.9 CHz with a 0.01 dB ripple level. The coupled line type low-pass filter with strip line configuration was fabricated by using a high-temperature superconducting (HTS : YBa$_2$Cu$_3$O$_{7-{\delta}}$ thin film on MgO(100) substrate. Since the HTS coupled tine type low-pass filter was proposed with five attenuation poles in stop band such as 1.8, 2.5, 4, 5.5, 6.2 GHz. The fabricated low-pass filter has improved the attenuation characteristics up to seven times of the cutoff frequency.