• Title/Summary/Keyword: 고장 테스트

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FSM-based Programmable Built-ln Self Test for Flash Memory (플래시 메모리를 위한 유한 상태 머신 기반의 프로그래머블 자체 테스트)

  • Kim, Ji-Hwan;Chang, Hoon
    • Journal of the Institute of Electronics Engineers of Korea SD
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    • v.44 no.6 s.360
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    • pp.34-41
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    • 2007
  • We popose a programmed on-line to FSM-based Programmable BIST(Buit-In Self-Test) with selected command, to select a test algorithm from a predetermined set of algorithms that are built in the Flash memory BIST. Thus, the proposed scheme greatly simplifies the testing process. Besides, the proposed FSM-based Programmable BIST is more efficient in terms of circuit size and test data to be applied, and it requires less time to configure the Flash memory BIST. We also will develop a programmable Flash memory BIST generator that automatically produces Verilog code of the proposed BIST architecture for a given set of test algorithms. If experiment the proposed method, the proposed method will achieves a good flexibility with smaller circuit size compared with previous methods.

A Study on the Design of Testable CAM using MTA Code (MTA 코드를 적용한 Testable CAM 설계에 관한 연구)

  • 정장원;박노경;문대철
    • Journal of the Korean Institute of Telematics and Electronics C
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    • v.35C no.6
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    • pp.48-55
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    • 1998
  • In this work, the testable CAM(Content Addressable Memory) is designed to perform the test effectively by inserting the ECC(Error Checking Circuit) inside the CAM. The designed CAM has the circuit which is capable of testing the functional faults in read, write, and match operations. In general the test circuit inserted causes the increase of total circuit area, Thus this work, utilizes the new MTA code to reduce the overhead of an area of the built-in test circuit which has a conventional parallel comparator. The designed circuit was verified using the VHDL simulator and the layout was performed using the 0.8${\mu}{\textrm}{m}$ double metal CMOS process. About 30% reduction of a circuit area wad achieved in the proposed CAM using the XOR circuit

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A Method for Selecting Software Reliability Growth Models Using Partial Data (부분 데이터를 이용한 신뢰도 성장 모델 선택 방법)

  • Park, Yong Jun;Min, Bup-Ki;Kim, Hyeon Soo
    • KIPS Transactions on Software and Data Engineering
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    • v.4 no.1
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    • pp.9-18
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    • 2015
  • Software Reliability Growth Models (SRGMs) are useful for determining the software release date or additional testing efforts by using software failure data. It is not appropriate for a SRGM to apply to all software. And besides a large number of SRGMs have already been proposed to estimate software reliability measures. Therefore selection of an optimal SRGM for use in a particular case has been an important issue. The existing methods for selecting a SRGM use the entire collected failure data. However, initial failure data may not affect the future failure occurrence and, in some cases, it results in the distorted result when evaluating the future failure. In this paper, we suggest a method for selecting a SRGM based on the evaluation goodness-of-fit using partial data. Our approach uses partial data except for inordinately unstable failure data in the entire failure data. We will find a portion of data used to select a SRGM through the comparison between the entire failure data and the partial failure data excluded the initial failure data with respect to the predictive ability of future failures. To justify our approach this paper shows that the predictive ability of future failures using partial data is more accurate than using the entire failure data with the real collected failure data.

The Scan-Based BIST Architecture for Considering 2-Pattern Test (2-패턴 테스트를 고려한 스캔 기반 BIST 구조)

  • 손윤식;정정화
    • Journal of the Institute of Electronics Engineers of Korea SD
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    • v.40 no.10
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    • pp.45-51
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    • 2003
  • In this paper, a scan-based low power BIST (Built-In Self-Test) architecture is proposed. The proposed architecture is based on STUMPS, which uses a LFSR (Linear Feedback Shift Register) as the test generator, a MISR(Multiple Input Shift Register) as the reponse compactor, and SRL(Shift Register Latch) channels as multiple scan paths. In the proposed BIST a degenerate MISR structure is used for every SRL channel; this offers reduced area overheads and has less impact on performance than the STUMPS techniques. The proposed BIST is designed to support both test-per-clock and test-per-scan techniques, and in test-per-scan the total power consumption of the circuit can be reduced dramatically by suppressing the effects of scan data on the circuits. Results of the experiments on ISCAS 89 benchmark circuits show that this architecture is also suitable for detecting path delay faults, when the hamming distance of the data in the SRL channel is considered.

Time-Series Neural Network Modeling of Pulsed Ion Energy Pattern and Applications to Plasma Monitoring (펄스드 이온에너지 패턴의 신경망 시계열 모델링과 플라즈마 감시에의 응용)

  • Kim, Su-Yeon;Kim, Byung-Whan
    • Proceedings of the KIEE Conference
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    • 2008.07a
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    • pp.1855-1856
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    • 2008
  • 본 연구에서는 공정 중에 민감하게 반응하는 플라즈마로부터 수집되는 이온에너지 분포(IED : Ion Energy Distribution)와 시계열 신경망 모델링을 결합한 플라즈마 감시 기술을 개발하였다. NIEA(Non-invasive ion analyzer)를 이용하여 IED를 측정하였으며, 모델링에 사용된 신경망은 자기 상관 시계열 신경망(A-NTS : Auto-Correlated Neural Time-Series)이다. 모델 개발을 위한 학습과 테스트 데이터로는 Duty ratio 100%에서 수집한 IED를 이용하였으며, 개발된 모델의 감시 성능은 60%에서 수집된 IED로 평가하였다. 학습인자 k와 m의 범위는 각각 1-3 으로 총 9종류의 (k, m) 조합에 대해서 모델 성능을 평가하였다. 신경망 은닉층 뉴런수는 2-9의 범위에서 최적화하였다. 최적화된 모델은 (2, 3)과 뉴런수 2에서 구해졌으며, 0.335의 예측 에러를 보였다. 60% IED 데이터로 평가한 결과 플라즈마 고장에의 민감도는 62% 이상이었다. 이는 IED의 A-NTS 모델이 플라즈마 고장의 감시에 효과적으로 적용될 수 있음을 의미한다.

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Test Pattern Genration for Detection of Stuck-Open and Stuck-On Faults in BiCMOS Circuits (BiCMOS 회로의Stuck-Open 고장과 Stuck-On 고장 검출을 위한 테스트 패턴 생성)

  • 신재흥;임인칠
    • Journal of the Korean Institute of Telematics and Electronics C
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    • v.34C no.1
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    • pp.1-11
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    • 1997
  • A BiCMOS circuit consists of the CMOS part which performs the logic function, and the bipolar part which drives output load. In BiCMOS circuits, transistor stuck-open faults exhibit delay faults in addition to sequential beavior. Also, stuck-on faults enhanced IDDQ (quiscent power supply current) at steady state. In this paper, a method is proposed which efficiently generates test patterns to detect stuck-open faults and stuck-on faults in BiCMOS circuits. The proposed method divides the BiCMOS circuit into pull-up part and pull-down part, and generates test patterns detect faults occured in each part by structural property of the BiCMOS circuit.

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The Comparative Study for ENHPP Software Reliability Growth Model based on Modified Coverage Function (변형 커버리지 함수를 고려한 ENHPP 소프트웨어 신뢰성장 모형에 관한 비교 연구)

  • Kim, Hee-Cheul;Kim, Pyong-Koo
    • Journal of the Korea Society of Computer and Information
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    • v.12 no.6
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    • pp.89-96
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    • 2007
  • Finite failure NHPP models presented in the literature exhibit either constant. monotonic increasing or monotonic decreasing failure occurrence rates per fault. Accurate predictions of software release times. and estimation of the reliability and availability of a software product require quality of a critical element of the software testing process : test coverage. This model called Enhanced non-homogeneous Poission process(ENHPP). In this paper, exponential coverage and S-type model was reviewed, proposes modified(the superosition and mixture) model, which make out efficiency application for software reliability. Algorithm to estimate the parameters used to maximum likelihood estimator and bisection method. model selection based on SSE statistics for the sake of efficient model, was employed.

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The Study for ENHPP Software Reliability Growth Model based on Superposition Coverage Function (중첩커버리지 함수를 고려한 ENHPP 소프트웨어 신뢰성장 모형에 관한 연구)

  • Kim, Hee-Cheul;Shin, Hyun-Cheul
    • Convergence Security Journal
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    • v.7 no.3
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    • pp.7-13
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    • 2007
  • Finite failure NHPP models presented in the literature exhibit either constant, monotonic increasing or monotonic decreasing failure occurrence rates per fault. Accurate predictions of software release times, and estimation of the reliability and availability of a software product require quantification of a critical element of the software testing process : test coverage. This model called Enhanced non-homogeneous poission process (ENHPP). In this paper, exponential coverage and S-shaped model was reviewed, proposes the superposition model, which maked out efficiency application for software reliability. Algorithm to estimate the parameters used to maximum likelihood estimator and bisection method, model selection based on SSE statistics for the sake of efficient model, was employed.

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SoC Design of Self-Diagnosing Speaker Connection System (자동 고장진단이 가능한 스피커 연결 시스템의 SoC 설계)

  • Song, Moon-Vin;Kwon, Oh-Kyun;Song, The-Hoon;Chung, Yun-Mo
    • The Journal of the Acoustical Society of Korea
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    • v.26 no.6
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    • pp.269-275
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    • 2007
  • Pervasive Multi-channel audio systems are being realized due to advances in digital technology. This paper proposes an efficient system that serially connects individual speakers with bidirectional digital communication capability by means of SoC design. In particular, each speaker can identify the bit stream assigned to the speaker and convert it into analog audio. Furthermore, the speaker can self-diagnose the speaker functionality by utilizing the designed capability to measure frequencies of various square wave test signals. The proposed system running on 200MHz clock yielded restoration of analog output signal with latency of only $500{\mu}s$ compared to directly driving the speakers in a traditional way.

Assessing Infinite Failure Software Reliability Model Using SPC (Statistical Process Control) (통계적 공정관리(SPC)를 이용한 무한고장 소프트웨어 신뢰성 모형에 대한 접근방법 연구)

  • Kim, Hee Cheul;Shin, Hyun Cheul
    • Convergence Security Journal
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    • v.12 no.6
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    • pp.85-92
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    • 2012
  • There are many software reliability models that are based on the times of occurrences of errors in the debugging of software. It is shown that it is possible to do asymptotic likelihood inference for software reliability models based on infinite failure model and non-homogeneous Poisson Processes (NHPP). For someone making a decision about when to market software, the conditional failure rate is an important variables. The finite failure model are used in a wide variety of practical situations. Their use in characterization problems, detection of outliers, linear estimation, study of system reliability, life-testing, survival analysis, data compression and many other fields can be seen from the many study. Statistical Process Control (SPC) can monitor the forecasting of software failure and there by contribute significantly to the improvement of software reliability. Control charts are widely used for software process control in the software industry. In this paper, we proposed a control mechanism based on NHPP using mean value function of log Poission, log-linear and Parto distribution.