• Journal of the Institute of Electronics Engineers of Korea SC
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• v.39 no.1
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• pp.66-75
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• 2002

For the theoretical performance analysis of Viterbi Decoder for wireless LAN with data rate 12Mbps, code rate 1/2 and constraint length 7 defined in IEEE 802.11a, the transfer function is derived using Cramer's rule and the first-event error probability and bit error probability is derived under the AWGN. In the design process, input symbol is quantized into 16 steps for 4 bit soft decision and register exchange method instead of memory method is proposed for trace back, which enables the majority at the final decision stage. In the implementation, the Viterbi decoder based on parallel architecture with pipelined scheme for processing 12Mbps high speed data rate and AWGN generator are implemented using FPGA chips. And then its performance is verified in real time.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.18 no.10
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• pp.1433-1443
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• 1993

DCT(Discrete Cosine Transform) / IDCT(Inverse DCT) is widely used in various image compression and decompression systems as well as in DSP(Digital Signal Processing) applications. Since DCT/ IDCT is one of the most complicated part of the compression system, the performance of the system can be greatly enchanced by improving the speed of DCT/IDCT operation. In this thesis, we designed a DCT/IDCT core processor using module generator technique. By utilizing the partial sum and DA(Distributed Arithmetic) techniques, the DCT/ IDCT core processor is designed within small area. It is also designed to perform the IDCT(Inverse DCT) operation with little additional circuitry. The pipeline structure of the core processor enables the high performance, and the high accuracy of the DCT/IDCT operation is obtained by having fewer rounding stages. The proposed design is independent of design rules, and the number of the input bits and the accuracy of the internal calculation coa be easily adjusted due to the module generator technique. The accuracy of the processor satisfies the specifications in CCITT recommendation H, 261.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.7 no.5
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• pp.893-898
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• 2003

This paper proposes a Truncated Type-II Hybrid ARQ scheme and coding techniques using an adaptive modulation system to achieve high throughput data transmission systems for wireless multimedia communication systems. In this paper, the adaptive modulation system analyzed in Nakagami (m-distribution) fading channel environment. The adaptive modulation system controls the modulation level and symbol rate according to the Nakagami fading parameter(m). When the received Eb/No is high or the Nakagami fading parameter m is high, the propose system selects higher modulation level and higher symbol rate to increase throughput. On the other hand, this system selects lower modulation level and lower symbol rate to prevent throughput performance degradation when the received Eb/No is low. The modulation method have been adopted QPSK(Quadrature Phase Shift Keying), 16QAM(Quadrature Amplitude Modulation), 64QAM, 256QAM. Therefore, adaptive modulation systems with truncated type-II hybrid ARQ scheme is proper for wireless multimedia communication system that require high reliability and delay-limited applications.

• Journal of the Korean Institute of Telematics and Electronics D
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• v.35D no.10
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• pp.107-115
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• 1998

A multiplier bit-pair recoding technique derived from Booth algorithm is used as an effective method that can carry out a fast binary multiplication regardless of a sign of both multiplicand and multiplier. In this paper, we propose an implementation of an optical high-speed multiplier which consists of a symbolic substitution adder and an optical multiplication algorithm, which transforms and enhances the multiplier bit-pair recoding algorithm to be fit for optical characteristics. Specially, a symbolic substitution addition rules are coded with a dual-rail logic, and so the complement of the logic of the symbolic substitution adder is easily obtained with a shift operation because it is always present. We also construct the symbolic substitution system which makes superposition image by superimposing two shifted images in a serial connection and recognizes a reference image by feeding this superimposed image to a mask. Thus, the optical multiplier, which is compared with a typical system, is implemented to the smaller system by reducing the number of optical passive elements and the size of this system.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.42 no.6 s.336
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• pp.39-48
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• 2005

This paper proposes a reconfigurable coprocessor for communication systems, which can perform high speed computations and various functions. The proposed reconfigurable coprocessor can easily implement communication operations, such as scrambling, interleaving, convolutional encoding, Viterbi decoding, FFT, etc. The proposed architecture has been modeled by VHDL and synthesized using the SEC 0.18$\mu$m standard cell library. The gate count is about 35,000 gates and the critical path is 3.84ns. The proposed coprocessor can reduced about $33\%$ for FFT operations and complex MAC, $37\%$ for Viterbi operations, and $48\%\~84\%$ for scrambling and convolutional encoding for the IEEE 802.11a WLAN standard compared with existing DSPs. The proposed coprocessor shows Performance improvements compared with existing DSP chips for communication algorithms.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.17 no.12 s.115
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• pp.1164-1171
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• 2006

In this paper, a simple and nonlinear MMSE detector is derived from the conventional linear MMSE detector to improve the system performance in turbo processing MIMO system and a new turbo processing MIMO system with nonlinear MMSE detector and Gaussian approximation is proposed. In turbo coded turbo processing MIMO system, the proposed system of M=N=4 performs about 0.5 dB better than the conventional system and the proposed system of M=N=8 performs about 0.4 dB better than conventional system at 1 % FER. In addition, the average number of outer iterations of proposed system shows lower than that of conventional system. This is caused by the fact that the nonlinear MMSE detector of proposed system decides soft-outputs of coded bits based on the observation of received signals, so that it can reduce the uncertainty region in estimating the coded bits.

• Journal of the Korea Academia-Industrial cooperation Society
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• v.11 no.1
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• pp.141-150
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• 2010

In this paper, performance of a turbo-coded OFDM system is analyzed and simulated in a power line communication channel. Since the power line communication system typically operates in a hostile environment, turbo code has been employed to enhance reliability of transmitted data. The performance is evaluated in terms of bit error probability. As turbo decoding algorithms, MAP (maximum a posteriori), Max-Log-MAP, and SOVA (soft decision viterbi output) algorithms are chosen and their performances are compared. From simulation results, it is demonstrated that Max-Log-MAP algorithm is promising in terms of performance and complexity. It is shown that performance is improved 3dB by increasing the number of iterations, 2 to 8, and interleaver length of a turbo encoder, 100 to 5000. The results in this paper can be applied to OFDM-based high-speed power line communication systems.

• Journal of the Korea Computer Industry Society
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• v.10 no.5
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• pp.227-234
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• 2009

The Paper introduces a new technique for block matching motion estimation. since the temporal correlation of a animation sequence between the motion vector of current block and the motion vector of previous block. In this paper, we propose the scene change detection algorithm for block matching using the temporal correlation of the animation sequence and the center-biased property of motion vectors. The proposed algorithm determines the location of a better starting point for the search of an exact motion vector using the point of the smallest SAD(sum of absolute difference) value by the predicted motion vector from the same block of the previous frame and the predictor candidate point on each search region. Simulation results show that the PSNR values are improved as high as 9~32% in terms of average number of search point per motion vector estimation and improved about 0.06~0.21dB on an average except the FS(full search) algorithm.

• Journal of the Institute of Electronics Engineers of Korea SP
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• v.48 no.1
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• pp.64-70
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• 2011

In an H.264/AVC video encoder, the motion estimation at fractional pixel accuracy improves a coding efficiency and image quality. However, it requires additional computation overheads for fractional search and interpolation, and thus, reducing the computation complexity of fractional search becomes more important. This paper proposes a Pixel Re-composition Fractional Motion Estimation (PRFME) algorithm for an H.264/AVC video encoder. Fractional Motion Estimation performs interpolation for the overlapped pixels which increases the computational complexity. PRFME can reduce the computational complexity by eliminating the overlapped pixel interpolation. Compared with the fast full search, the proposed algorithm can reduce 18.1% of computational complexity, meanwhile, the maximum PSNR degradation is less than 0.067dB. Therefore, the proposed PRFME algorithm is quite suitable for mobile applications requiring low power and complexity.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.8 no.7
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• pp.1405-1409
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• 2004

This paper is studied new block mode decision algorithm for H.264/AVC. The fast block mode decision algorithm is consist of block range decision algorithm. The block range decision algorithm classifies the block over 8$\times$8 size or below for 16${\times}$16 macroblock to decide the size and type of sub blocks. As the sub blocks of 8$\times$8, 8r4, 4$\times$8 and 4$\times$4, which are the blocks below 8$\times$8 size, include important motion information, the exact sub block decision is required. RDC(RDO cost) is used as the matching parameter for the exact sub block decision. RDC is calculated with motion strength which is the mean value of neighbor pixels of each sub block. The sub block range decision reduces encoding arithmetic amount by 34.62% on the average more than the case not using block range decision. The block mode decision using motion strength shows improvement of PSNR of 0.05[dB].