• Journal of Sensor Science and Technology
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• v.31 no.4
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• pp.271-277
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• 2022

We analyzed the effects of the interface trap on the output characteristics of an inversion mode n-channel GaN Schottky barrier (SB)-MOSFET based on the N_it distribution using TCAD simulation. As interface trap number density (N_it) increased, the threshold voltage increased while the drain current density decreased. Under N_it=5.0×10¹⁰ cm^-2 condition, the threshold voltage was 3.2 V for V_DS=1 V, and the drain current density reduced to 2.4 mA/mm relative to the non-trap condition. Regardless of the N_it distribution type, there was an increase in the subthreshold swing (SS) following an increase in N_it. Under U-shaped N_it distribution, it was confirmed that the SS varied depending on the gate voltage. The interface fixed charge (Q_f) caused an shift in the threshold voltage and increased the off-state current collectively with the surface trap. In summary, GaN SB-MOSFET can be a building block for high power UV optoelectronic circuit provided the surface state is significantly reduced.

• Journal of IKEEE
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• v.27 no.4
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• pp.418-424
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• 2023

In this study, we examined the effects of annealing on electrical characteristics of double-gated silicon nanosheet (SiNS) feedback field effect transistors (FBFETs). When bias stresses were applied for 1000 s, the double-gated SiNS FBFETs were more affected by positive bias stresses than negative bias stresses regardless of the channel mode owing to the increase of interface traps caused by electrons in the inversion layers. After annealing at 300 ℃ for 10 mins, the devices were completely recovered to their original properties, and the characteristics did not change anymore when bias stresses were applied again for 1000 s.

• Journal of the Korean Vacuum Society
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• v.7 no.4
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• pp.341-347
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• 1998

We analyzed photoreflectance (PR) characterization of the $Al_xGa_{1-x}As$ epilayer grown by molecular beam epitaxy (MBE) method. The band-gap energy $(E_0)$ satisfying low power Franx-Keldysh (LPFK) due to GaAs buffer layer is 1.415 eV, interface electricall field $(E_i)$ is 1.05$\times$$10^4$V/cm, carrier concentration (N) is $1.3{\times}10^{15}\textrm{cm}^{-3}$. In PR spectrum intensity analysis at 300 K the $A^*$ peak below $(E_0)$ signal is low and distorted because of residual impurity in sample growth. The trap characteristic time ${\tau}_i$ of GaAs buffer layer is about 0.086 ms, and two superposed PR signal near 1.42eV consist of the third derivative signal of chemically eteched GaAs substrate and Franz-Keldysh oscillation (FKO) signal due to GaAs buffer layer.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.13 no.11
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• pp.914-920
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• 2000

When the charge-trap type SONOS(polysilicon-oxide-nitride-oxide-semiconductor) cells are used to flash memory, the tunneling program/erase condition to minimize the generation of interface traps was investigated. SONOSFET NVSM(Nonvolatile Semiconductor Memory) cells were fabricated using 0.35 ㎛ standard memory cell embedded logic process including the ONO cell process, based on retrograde twin-well, single-poly, single metal CMOS(Complementary Metal Oxide Semiconductor) process. The thickness of ONO triple-dielectric for the memory cell is tunnel oxide of 24 $\AA$, nitride of 74 $\AA$, blocking oxide of 25 $\AA$, respectively. The program mode(V$\_$g/=7, 8, 9 V, V$\_$s/=V$\_$d/=-3 V, V$\_$b/=floating) and the erase mode(V$\_$g/=-4, -5, -6 V, V$\_$s/=V$\_$d/=floating, V$\_$b/=3 V) by MFN(Modified Fowler-Nordheim) tunneling were used. The proposed programming condition for the flash memory of SONOSFET NVSM cells showed less degradation(ΔV$\_$th/, S, G$\_$m/) characteristics than channel MFN tunneling operation. Also, the program inhibit conditins of unselected cell for separated source lines NOR-type flash memory application were investigated. we demonstrated that the phenomenon of the program disturb did not occur at source/drain voltage of 1 V∼12 V and gate voltage of -8 V∼4 V.

• Journal of Sensor Science and Technology
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• v.12 no.5
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• pp.218-224
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• 2003

The devices of n-channel poly silicon thin film transistors(TFTs) hydrogenated by plasma, $H_2$ and $H_2$/plasma processes are fabricated. The carriers sensitivity characteristics are analyzed with voltage bias stress at the gate oxide. The parametric sensitivity characteristics caused by electrical stress conditions in hydrogenated devices are investigated by measuring the drain current, threshold voltage($V_{th}$), subthreshold slope(S) and maximum transconductance($G_m$) values. As a analyzed results, the degradation characteristics in hydrogenated n-channel polysilicon thin film transistors are mainly caused by the enhancement of dangling bonds at the poly-Si/$SiO_2$ interface and the poly-Si grain boundary due to dissolution of Si-H bonds. The generation of traps in gate oxide are mainly dued to hot electrons injection into the gate oxide from the channel region.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2007.11a
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• pp.94-95
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• 2007

In this paper, the dependence of electrical characteristics of Silicon-$Al_2O_3$-Nitride-Oxide-Silicon (SANOS) memory cell transistors and program speed, reliability of memory device on interface trap between Si substrate and tunneling oxide was investigated. The devices were fabricated by the identical processing in a single lot except the deposition method of the charge trapping layer, nitride. In the case of P/E speed, it was shown that P/E speed is slower in the SONOS cell transistors with larger interface trap density by charge blocking effect, which is confirmed by simulation results. However, the data retention characteristics show much less dependence on interface trap. Therefore, to improve SANOS memory characteristic, it is very important to optimize the interface trap and charge trapping layer.

• Journal of the Korean Vacuum Society
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• v.12 no.4
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• pp.239-250
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• 2003

The reliability degradation phenomena in the SiGe hetero-junction bipolar transistor (HBT) are investigated in this review. In the case of the SiGe HBT the decrease of the current gain, the degradation of the AC characteristics, and the offset voltage are frequently observed, which are attributed to the emitter-base reverse bias voltage stress, the transient enhanced diffusion, and the deterioration of the base-collector junction due to the fluctuation in fabrication process, respectively. The reverse-bias stress on the emitter-base junction causes the recombination current to rise, increasing the base current and degrading the current gain, because hot carriers formed by the high electric field at the junction periphery generate charged traps at the silicon-oxide interface and within the oxide region. Because of the enhanced diffusion of the dopants in the intrinsic base induced by the extrinsic base implantation, the shorter distance between the emitter-base junction and the extrinsic base than a critical measure leads to the reduction of the cut-off frequency ($f_t$) of the device. If the energy of the extrinsic base implantation is insufficient, the turn-on voltage of the collector-base junction becomes low, in the result, the offset voltage appears on the current-voltage curve.

• Journal of the Korea Academia-Industrial cooperation Society
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• v.20 no.6
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• pp.14-18
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• 2019

The conductivity of a semiconductor is primarily determined by the carriers. To achieve higher conductivity, the number of carriers should be high, and an energy trap level is created so that the carriers can cross the forbidden zone with low energy. Carriers have a crystalline binding structure, and interfacial mismatching tends to make them less conductive. In general, high-concentration doping is typically used to increase mobility. However, higher conductivity is also observed in non-orthogonal conjugation structures. In this study, the phenomena of higher conductivity and higher mobility were observed with space charge limiting current due to tunneling phenomena, which are different from trapping phenomena. In an atypical structure, the number of carriers is low, the resistance is high, and the on/off characteristics of capacitances are improved, thus increasing the mobility. ZTO thin film improved the on/off characteristics of capacitances after heat treating at $150^{\circ}C$. In charging and discharging tests, there was a time difference in the charge and discharging shapes, there was no distinction between n and p type, and the bonding structure was amorphous, such as in the depletion layer. The amorphous bonding structure can be seen as a potential barrier, which is also a source of space charge limiting current and causes conduction as a result of tunneling. Thus, increased mobility was observed in the non-structured configuration, and the conductivity increased despite the reduction of carriers.