• Journal of the Korea Institute of Information and Communication Engineering
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• v.21 no.7
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• pp.1276-1284
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• 2017

Lightweight Encryption Algorithm (LEA) that was standardized as a lightweight block cipher was implemented with 8-bit data path, and the vulnerability of LEA encryption processor to correlation power analysis (CPA) attack was analyzed. The CPA used in this paper detects correct round keys by analyzing correlation coefficient between the Hamming distance of the computed data by applying hypothesized keys and the power dissipated in LEA crypto-processor. As a result of CPA attack, correct round keys were detected, which have maximum correlation coefficients of 0.6937, 0.5507, and this experimental result shows that block cipher LEA is vulnerable to power analysis attacks. A masking method based on TRNG was proposed as a countermeasure to CPA attack. By applying masking method that adds random values obtained from TRNG to the intermediate data of encryption, incorrect round keys having maximum correlation coefficients of 0.1293, 0.1190 were analyzed. It means that the proposed masking method is an effective countermeasure to CPA attack.

• Convergence Security Journal
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• v.5 no.3
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• pp.23-32
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• 2005

This paper presents a 128-bit Reversible Cellular Automata (RCA) based lightweight block cipher for Ubiquitous computing security. To satisfy resource-constraints for Ubiquitous computing, it is designed as block architecture based on Cellular Automata with high pseudo-randomness. Our implementation requires 704 clock cycles and consumes 2,874 gates for encryption of a 128-bit data block. In conclusion, the processing time outperformed that of AES and NTRU by 31%, and the number of gate was saved by 20%. We evaluate robustness of our implementation against both Differential Cryptanalysis and Strict Avalanche Criterion.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.20 no.7
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• pp.1296-1302
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• 2016

A hardware implementation of ultra-lightweight block cipher algorithm PRESENT that was specified as a block cipher standard for lightweight cryptography ISO/IEC 29192-2 is described in this paper. Two types of crypto-core that support master key size of 80-bit are designed, one is for encryption-only function, and the other is for encryption and decryption functions. The designed PR80 crypto-cores implement the basic cipher mode of operation ECB (electronic code book), and it can process consecutive blocks of plaintext/ciphertext without reloading master key. The PR80 crypto-cores were designed in soft IP with Verilog HDL, and they were verified using Virtex5 FPGA device. The synthesis results using $0.18{\mu}m$ CMOS cell library show that the encryption-only core has 2,990 GE and the encryption/decryption core has 3,687 GE, so they are very suitable for IoT security applications requiring small gate count. The estimated maximum clock frequency is 500 MHz for the encryption-only core and 444 MHz for the encryption/decryption core.

• Journal of Korea Multimedia Society
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• v.12 no.5
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• pp.644-652
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• 2009

New communication environments such as USN, WiBro and RFID have been realized nowadays. Thus, in order to ensure security and privacy protection, various light-weight block ciphers, e.g., mCrypton, HIGHT, SEA and PRESENT, have been proposed. The block cipher mCrypton, which is a light-weight version of Crypton, is a 64-bit block cipher with three key size options (64 bits, 96 bits, 128 bits). In this paper we show that 8-round mCrypton with 128-bit key is vulnerable to related-key rectangle attack. It is the first known cryptanalytic result on mCrypton. We first describe how to construct two related-key truncated differentials on which 7-round related-key rectangle distinguisher is based and then exploit it to attack 8-round mCrypton. This attack requires $2^{45.5}$dada and $2^{45.5}$time complexities which is faster than exhaustive key search.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.20 no.2
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• pp.351-358
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• 2016

This paper describes an efficient hardware implementation of lightweight block cipher algorithm CLEFIA. The CLEFIA crypto-processor supports for three master key lengths of 128/192/256-bit, and it is based on the modified generalized Feistel network (GFN). To minimize hardware complexity, a unified processing unit with 8 bits data-path is designed for implementing GFN that computes intermediate keys to be used in round key scheduling, as well as carries out round transformation. The GFN block in our design is reconfigured not only for performing 4-branch GFN used for round transformation and intermediate round key generation of 128-bit, but also for performing 8-branch GFN used for intermediate round key generation of 256-bit. The CLEFIA crypto-processor designed in Verilog HDL was verified by using Virtex5 XC5VSX50T FPGA device. The estimated throughput is 81.5 ~ 60 Mbps with 112 MHz clock frequency.

• Journal of the Korea Institute of Information Security & Cryptology
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• v.30 no.3
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• pp.325-336
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• 2020

Nonlinear Invariant Attack is an attack that should be considered when constructing lightweight block ciphers with relatively simple key schedule. A shortcut to prove a block cipher's resistance against nonlinear invariant attack is checking the smallest dimension of linear layer-invariant linear subspace which contains all known differences between round keys is equal to the block size. In this paper, we presents the following results. We identify the structure and number of optimal bit-permutations which require only one known difference between round keys for a designer to show that the corresponding block cipher is resistant against nonlinear invariant attack. Moreover, we show that PRESENT-like block ciphers need at least two known differences between round keys by checking all PRESENT-like bit-permutations. Additionally, we verify that the variants of PRESENT-like bit-permutations requiring the only two known differences between round keys do not conflict with the resistance against differential attack by comparing the best differential trails. Finally, through the distribution of the invariant factors of all bit-permutations that maintain BOGI logic with GIFT S-box, GIFT-variant block ciphers require at least 8 known differences between round keys for the resistance.

• Smart Media Journal
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• v.4 no.4
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• pp.39-46
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• 2015

This paper describes hardware implementation of the encryption block of the '128 bit block cipher LEA' among various lightweight encryption algorithms for IoT (Internet of Things) security. Round function blocks and key-schedule blocks are designed by parallel circuits for high throughput. The encryption blocks support secret-key of 128 bits, and are designed by FSM method and 24/n stage(n=1, 2, 3, 4, 8, 12) pipeline methods. The LEA-128 encryption blocks are modeled using Verilog-HDL and implemented on FPGA, and according to the synthesis results, minimum area and maximum throughput are provided.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2015.10a
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• pp.409-411
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• 2015

본 논문은 128/192/256-비트의 마스터키 길이를 지원하는 경량 블록 암호 알고리즘 CLEFIA-128/192/256의 FPGA 설계에 대하여 기술한다. 라운드키 생성을 위한 중간키 생성과 라운드 변환이 단일 데이터 프로세싱 블록으로 처리되도록 설계하였으며, 변형된 GFN(Generalized Feistel Network) 구조와 키 스케줄링 방법을 적용하여 데이터 프로세싱 블록과 키 스케줄링 블록의 회로를 단순화시켰다. Verilog HDL로 설계된 CLEFIA 크립토 프로세서를 FPGA로 구현하여 정상 동작함을 확인하였다. Vertex5 XC5VSX50T FPGA에서 1,563개의 LUT FilpFlop pairs로 구현되었으며, 최대 112 Mhz 81.5/69/60 Mbps의 성능을 갖는 것으로 예측되었다.

• Proceedings of the Korea Information Processing Society Conference
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• 2020.11a
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• pp.405-408
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• 2020

양자 컴퓨터를 활용한 양자 알고리즘은 우리가 현재 사용하고 있는 많은 암호들의 안전성을 깨뜨릴 수 있다. 그루버 알고리즘을 n-bit 보안레벨을 가지는 대칭키 암호에 적용한다면 보안레벨을 O(2^n/2)까지 낮출 수 있다. 그루버 알고리즘을 적용하기 위해서는 우선 대상 암호가 양자 회로로 구현되어야 한다. 때문에 대상 블록암호를 양자 회로로 최적화하는 연구들이 최근 활발히 진행되고 있다. 이에 본 논문에서는 국산 경량 블록암호 LEA를 양자 회로에서 최적화 하였다. 기존의 LEA 양자 회로구현과 비교하여 양자 게이트는 더 많이 사용하였지만, 큐빗을 획기적으로 줄일 수 있었으며 이에 대한 성능 평가를 수행하였다. 마지막으로 제안하는 LEA 구현에 그루버 알고리즘을 적용하기 위한 양자 자원을 평가하였다.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.20 no.6
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• pp.1163-1170
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• 2016

A hardware implementation of ultra-lightweight block cipher algorithm PRESENT which was specified as a standard for lightweight cryptography ISO/IEC 29192-2 is described. The PRESENT crypto-processor supports two key lengths of 80 and 128 bits, as well as four modes of operation including ECB, CBC, OFB, and CTR. The PRESENT crypto-processor has on-the-fly key scheduler with master key register, and it can process consecutive blocks of plaintext/ciphertext without reloading master key. In order to achieve a lightweight implementation, the key scheduler was optimized to share circuits for key lengths of 80 bits and 128 bits. The round block was designed with a data-path of 64 bits, so that one round transformation for encryption/decryption is processed in a clock cycle. The PRESENT crypto-processor was verified using Virtex5 FPGA device. The crypto-processor that was synthesized using a $0.18{\mu}m$ CMOS cell library has 8,100 gate equivalents(GE), and the estimated throughput is about 908 Mbps with a maximum operating clock frequency of 454 MHz.