• Journal of the Korean Crystal Growth and Crystal Technology
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• v.24 no.5
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• pp.190-195
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• 2014

Because of the temperature gradient occurring during the growth of the ingot with directional solidification method, defects are generated and the residual stress is produced in the ingot. Changing the growth and cooling rate during the crystal growth process will be helpful for us to understand the defects and residual stress generation. The defects and residual stress can affect the properties of wafer. Generally, it was found that the size of grains and twin boundaries are smaller at the top area than at the bottom of the ingot regardless of growth and cooling condition. In addition to that, in the top area of silicon ingot, higher density of dislocation is observed to be present than in the bottom area of the silicon ingot. This observation implies that higher stress is imposed to the top area due to the faster cooling of silicon ingot after solidification process. In the ingot with slower growth rate, dislocation density was reduced and the TTV (Total Thickness Variation), saw mark, warp, and bow of wafer became lower. Therefore, optimum growth condition will help us to obtain high quality silicon ingot with low defect density and low residual stress.

• Proceedings of the Materials Research Society of Korea Conference
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• 1994.05a
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• pp.154-154
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• 1994

• Proceedings of the Korean Powder Metallurgy Institute Conference
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• 1995.11a
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• pp.27-28
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• 1995

• Journal of the Korean Crystal Growth and Crystal Technology
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• v.12 no.4
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• pp.172-177
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• 2002

The CuZnAl alloys have some advantages against other shape memory alloys, such as the widely variable transformation temperature, the low cost and easy fabrication. The alloys have been produced mostly by metallurgical methods. Thereby a tendency to large grain sizes is observed, which causes brittle properties of the materials. In order to avoid these deficiencies a special powder metallurgical process, SPS(spark plasma sintering), is applied in the present investigation. The starting materials were the pure (99.9 %) Cu, Zn and Al element powders with different particle size. The relatively fine grained and homogeneous Cu-24.78Zn-9.11Al (at.%) and Cu-13.22Zn-17.24Al (at.%) shape memory alloys were obtained using the powders with size of 75-150 $\mu$m. The average grain size is about 70 $\mu$m and the phases at room temperature are the austenitic and martensitic phase respectively.

• Journal of the Korean Institute of Illuminating and Electrical Installation Engineers
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• v.15 no.4
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• pp.57-61
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• 2001

The {111}<112> deformation torture, which originated from the {110}<00l> texture near the surface of hot bands, is not prerequisite for the recrystallized {110}<001> Goss texture. During final annealing, surface-energy-induced selective growth of grains urn at the strip surface of 3%Si-Fe alloys containing 6ppm bulk content of sulfur. With decreasing final reduction, the probability that Goss grains survive under the highly segregated sulfur atmosphere and have a chance for later surface-energy-induced selective growth becomes higher, resulting in high magnetic induction.

• Proceedings of the KWS Conference
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• 1998.05a
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• pp.144-146
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• 1998

• Proceedings of the Materials Research Society of Korea Conference
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• 2008.05a
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• pp.43.1-43.1
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• 2008

• Electrical & Electronic Materials
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• v.6 no.5
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• pp.446-453
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• 1993

초기충진압력이 서로 다른 시편에 가한 가압횟수와 열처리시간의 혼합공정이 임계전류밀도 특성에 미치는 영향을 관찰하기 위하여 power-in-tube방법으로 초전도 선재를 제조하였다. 일정 초기충진압력에서 테이프화를 위한 열처리 및 가압이 혼합공정횟수가 증가할수록 임계전류밀도가 증가하였다. 초기충진압력이 1000kg/$cm^{2}$에서 Bi-2223 고온상 체적비가 가장 높게 나타났고 결정립이 판상으로 성장되었을 뿐만 아니라 C축과 직각방향으로 잘 배양되어 있음을 관찰할 수 있었다. 특히 초기충진압력 1000kg/$cm^{2}$의 시편을 두께를 줄이기 위하여 3회 가압하고 450시간 열처리하였을때 임계전류밀도가 5800A/$cm^{2}$를 나타내었으며 이를 중심으로 500, 2500kg/$cm^{2}$이 양측단으로 가우시안분포를 보였다. 결론적으로 시편의 임계특성은 적정 초기충진압력, Bi-2223 고온상 체적비, 테이프화를 위한 가압횟수, 결정의 일방향배열, 결정립의 성장등에 강하게 의존함을 알 수 있었다.

• Journal of the Korean Crystal Growth and Crystal Technology
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• v.6 no.3
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• pp.386-391
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• 1996

SiC particles (average size is 270 nm) of 0, 10, 20, 30, 40 vol% were dispersed in $Si_{3}N_{4}$, and $Si_{3}N_{4}/SiC$ nanocomposites were fabricated by hot press. After sintering, matrix phase, ${\alpha}-Si_{3}N_{4}$ was transformed to ${\beta}-Si_{3}N_{4}$, and second phase, ${\beta}-SiC$ was not changed. No grain boundary crystalline phase by adding of sintering additives was detected. Grain growth of $Si_{3}N_{4}$ was supressed with increasing of SiC contents, and then fine grain was occurred. The highest fracture strength was obtained at 10 vol% SiC, and fracture toughness was decreased, but hardness was linearly increased with SiC content.

• Journal of the Korean Vacuum Society
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• v.4 no.2
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• pp.164-171
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• 1995

열처리에 따른 Cu 박막의 미세구조 및 전기 비저항의 변화를 조사하였다. Cu(hfac)(TMVS)를 원료로 하는 저압화학증착법에 의해 증착온도를 $160^{\circ}C$에서 $330^{\circ}C$까지 변화시키면서 TiN기판 위에 Cuqkr막을 제조하였고 $450^{\circ}C$에서 30분간 열처리하였다. 증착온도에 따라 표면이 평평한 Cu 박막을 형성하는 표면반응 제한지역과 표면이 거친 Cu 박막을 형성하는 물질전달제한지역이 관찰되었다. 열처리 후 Cu 박막은 전체적으로 표면이 평탄해졌고 결정립의 크기는 모든 증착온도에서 증가하였는데 그 편차 역시 증가하여 EM 저항성 측면에서는 큰 효과를 보이지 못할 것으로 판단된다. 비저항은 증착온도 $200^{\circ}C$에서 급격히 증가하였고 열처리 후에는 모든 증착온도에서 비저항이 감소하였는데 표면반응제한지역에서는 결정립 성장에 의한 약간의 비저항 감소를 보였으나 물질전달제한지역에서는 응집에 의해 Cu 결정립간의 전기적 연결상태가 향상되어 급격한 비저항 감소를 보였다.