• Proceedings of the Optical Society of Korea Conference
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• 2002.07a
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• pp.160-161
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• 2002

양자 암호화 키 분배 시스템에서 광자를 code화시키는 방법은 크게 편광coding과 위상 coding으로 대별할 수 있다. 또한 프로토콜은 4개의 상태를 가진 BB82 프로토콜과 2개의 상태를 가진 B92 프로토콜을 사용한 시스템을 많이 연구하고 있다. 본 연구는 B92프로토콜을 적용한, 위상 coding 양자 암호화 키 분배 시스템의 구성에 필요한 위상 변조기에 대한 비교 검토 및 위상 변조기 설계에 관한 것이다. (중략)

• Journal of the Korean Society for Nondestructive Testing
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• v.33 no.4
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• pp.376-381
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• 2013

위상잠금 열화상에서는 일반적으로 변조된 주파수의 광램프를 쓰고 있다. 하지만 램프의 광도 분포는 입력신호가 평단(flat)특성임에 불구하고 심지어 불균일하여 검사 시편내에 측면 열유동을 만들어낸다. 이러한 열유동은 원치 않는 효과로서 측면의 분해능을 감소시키는 등과 같이 관심 결함구조의 영상에 부정적인 영향을 미친다. 본 고에서 검토되는 방식은 열원으로서 LCD 프로젝터와 같은 것을 이용하여 각 가진픽셀에 개별적으로 진동진폭, 광도 오프셋, 위상지연 등을 할당하는 방법에 대한 접근기술이다. 이러한 반복적인 자체학습 과정에 의한 조명 패턴을 통하여 측면 열유동이 제거되고 분해능이 향상되도록 제공하는 것이다.

• The Journal of Korea Institute of Information, Electronics, and Communication Technology
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• v.11 no.3
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• pp.283-289
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• 2018

A PLL with an unipolar charge pump and a loop filter consisting of sample-hold capacitor and Fvco-sampled feedforward loop filter. The proposed PLL not only reduces the chip area by replacing the resistance to a switch and a small capacitor but also reduces the variation of ${\Delta}VLPF$ and ${\Delta}{\Delta}VLPF$ to 1/6 and 1/5 respectively. The variation of ${\Delta}VLPF$ is related to the phase noise of VCO output and that of ${\Delta}{\Delta}VLPF$ is proportional to reference spurs. It has been simulated and verified with a 1.8V $0.18{\mu}m$ CMOS process and shown a good phase noise characteristics. We plan to fabricate chip based on the simulations and check performance.

• Proceedings of the Korean Information Science Society Conference
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• 1999.10a
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• pp.201-203
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• 1999

지리정보시스템의 정보를 관리하는 공간데이터베이스 관리시스템에서는 위상정보에 대한 효율적인 저장과 관리가 필요하다. 이렇게 기하학적인 정보만을 가진 객체의 자료 구조에 위상정보를 추가하거나 또는 위상적인 정보만으로 이러한 지도를 만드는 작업을 위상정보 구축작업이라고 한다. 공간데이터베이스의 위상정보를 생성하는 작업은 많은 연산과 상당한 시간을 요구하므로 일종의 장기 트랜잭션이라 할 수 있다. 이런 위상정보 구축 트랜잭션은 위상적 데이터의 특성을 이용하면 기존에 제안된 방법보다 효과적으로 처리할 수 있다. 본 논문에서는 위상정보 생성시의 장기 트랜잭션을 위하여 정의한 위상구축 트랜잭션이 완전성을 유지하면서 하위 트랜잭션으로 나눌수 있도록 Plane-sweeping을 이용한 위상구축 알고리즘을 제안하였다. 이 방법을 이용하면 위상구축이 수행되는 동안에도 위상이 구축되어 있는 지역에 대한 질의의 결과를 보장할 수 있다.

• Korean Journal of Optics and Photonics
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• v.23 no.4
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• pp.135-142
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• 2012

We have developed a measurement method of the refractive index profile of an optical fiber by using diffraction phase microscopy. In the microscope system, the reference light was extracted directly from the probe light that passed through the sample by means of pinhole filtering with a diffraction grating. The spatial interference pattern produced by the probe light and the reference light was processed to generate the phase image of the sample fiber. The index profile was obtained by the inverse Abel transform of the phase profile. In order to remove the background phase that originated from the index difference between the cladding and the surrounding medium, the background phase was calculated from the phase data of the cladding to make a core phase profile that can be directly transformed to the index profile of the core without the full phase image that includes the entire cladding part.

• Journal of the Korean Society of Propulsion Engineers
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• v.22 no.2
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• pp.1-10
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• 2018

This study investigated the acoustic forcing effects on the liquid column breakup length and the trajectory of liquid jets in crossflows. Cold-flow tests with a single hole circular nozzle injector were carried out by changing the injection pressure and acoustic forcing amplitude. Additionally, spray images were obtained at 12 phase angles to investigate the influence of the phage angle. The results revealed that the liquid column breakup lengths generally decreased under the acoustic forcing conditions, in comparison to those under the non-acoustic forcing conditions. However, they were not affected by the variation in the phase angles. On the contrary, it was found that the acoustic forcing hardly influenced the liquid column trajectories.

• Journal of Astronomy and Space Sciences
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• v.10 no.2
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• pp.146-151
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• 1993

AZ Cas는 B형의 주계열 별과 확장 대기를 가진 만기형으로 이루어진 쌍성계이다. 근성점 근처에서 Roche lobe를 채운 초거성으로부터 일어나는 질량 흐름이 미치는 효과를 구하기 위해 궤도위상 0.05와 0.09에서 불투명도 계수에 따른 AZ Cas의 선윤곽을 계산하였다. 원천 함수는 Hempe(1982)의 방법을 따라 Sobolev 근사방법을 이용하였으며 불투명도 계수가 클수록 넓은 흡수 부분을 가진 강한 선윤곽을 보였다. 궤도 위상 0.05의 부분식이세 나타난 bump는 흡수선위에 포피의 산란에 의해 생긴 방출선이 중첩되어 나타난 재방출 효과인 것으로 설명된다.

• Journal of the Institute of Electronics and Information Engineers
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• v.50 no.10
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• pp.76-81
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• 2013

A new phase frequency detector based digital phase-locked loop (PLL) of 125 MHz was designed using the 130 nm CMOS technology library consisting of inverting edge detectors along with a typical digital phase-locked loop to reduce the lock time and jitter for mid-frequency applications. XOR based inverting edge detectors were used to obtain a transition earlier than the reference signal to change the output more quickly. The HSPICE simulator was used in a Cadence environment for simulation. The performance of the digital phase-locked loops with the proposed phase frequency detector was compared with that of conventional phase frequency detector. The PLL with the proposed detector took $0.304{\mu}s$ to lock with a maximum jitter of approximately 0.1142 ns, whereas the conventional PLL took a minimum of $2.144{\mu}s$ to lock with a maximum jitter of approximately 0.1245 ns.

• The Journal of Korea Institute of Information, Electronics, and Communication Technology
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• v.12 no.1
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• pp.1-6
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• 2019

An extremely small size multi-loop phase-locked loop(PLL) keeping phase noise performances has been proposed. It has been designed to have the loop filter made of small single capacitor with multiple Frequency Voltage Converters (FVCs) because the main goal is to make the size of the proposed PLL extremely small. Multiple FVCs which are connected to voltage controlled oscillator(VCO) make multiple negative feedback loops in PLL. Those multiple negative feedback loops enable the PLL with the loop filter made of an extremely small size single capacitor operate stably. It has been designed with a 1.8V $0.18{\mu}m$ CMOS process. The simulation results show that the proposed PLL has the 1.6ps jitter and $10{\mu}s$ locking time.

• The Journal of Korea Institute of Information, Electronics, and Communication Technology
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• v.14 no.6
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• pp.479-486
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• 2021

In this paper, an ultra small phase locked loop (PLL) with a single capacitor loop filter has been proposed by adding a signal sensing circuit (SSC). In order to extremely reduce the size of the PLL, the passive element loop filter, which occupies the largest area, is designed with a very small single capacitor (2pF). The proposed PLL is designed to operate stably by the output of the internal negative feedback loop including the SSC acting as a negative feedback to the output of the single capacitor loop filter of the external negative feedback loop. The SSC that detects the PLL output signal change reduces the excess phase shift of the PLL output frequency by adjusting the capacitance charge of the loop filter. Although the proposed structure has a capacitor that is 1/78 smaller than that of the existing structure, the jitter size differs by about 10%. The PLL is designed using a 1.8V 180nm CMOS process and the Spice simulation results show that it works stably.