• 한국전기전자재료학회논문지
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• 제22권1호
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• pp.29-34
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• 2009

PLZT thin films were deposited on platinized silicon (Pt/$TiSiO_2$/Si) substrate by RF magnetron sputtering. A $TiO_2$ buffer layer was fabricated, prior to deposition of PLZT films. the layer was strongly affected the crystallographic orientation of the PLZT films. X-ray diffraction was performed on the films to study the crystallization of the films as various substrate temperatures (Ts). According to increasing Ts, preferred orientation of films was changed (110) plane to (111) plane. The ferroelectric, dielectric and electrical properties of the films were also investigated in detail as increased substrate temperatures. The PLZT films deposited at $400^{\circ}C$ showed good ferroelectric properties with the remnant polarization of $15.8{\mu}C/cm^2$ and leakage current of $5.4{\times}10^{-9}\;A/cm^2$.

• 한국진공학회지
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• 제17권1호
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• pp.28-33
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• 2008

R.F 마그네트론 스퍼터링 방법을 이용하여 Indium tin oxide(ITO)가 증착된 유리기판 위에 PLZT ($Pb_{1.1}La_{0.08}Zr_{0.65}Ti_{0.35}O_3$) 박막을 제작하였다. 기판온도를 $500^{\circ}C$로 고정하여 증착한 후 급속열처리 방법으로 다양한 온도 ($550-750^{\circ}C$)에서 후열처리 하였다. 후열처리온도의 변화에 따른 PLZT 박막의 결정학적 특성을 X선 회절법을 통하여 분석하였고 원자간력 현미경을 이용하여 박막의 표면 상태를 관찰하였다. 또한 precision material analyzer 을 이용하여 분극이력곡선과 피로특성을 측정하였다. 후 열처리 온도가 증가함에 따라 잔류분극 값(Pr)은 $10.6{\mu}C/cm^2$ 에서 $31.4{\mu}C/cm^2$로 증가하였으며 항전계(Ec)는 79.9 kV/cm에서 60.9 kV/cm로 감소하는 경향을 보였다. 또한 피로특성의 경우 1MHz 주파수에서 ${\pm}5V$의 square wave를 인가하여 측정한 결과 $700^{\circ}C$에서 후열처리한 시편의 경우 $10^9$회 이상의 분극반전을 거듭하였을 때 분극값이 15% 감소하는 결과를 나타내었다.

• 한국전기전자재료학회논문지
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• 제32권2호
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• pp.174-177
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• 2019

The traditional yttria-stabilized zirconia (YSZ) used in thermal barrier coatings has a limited operating temperature owing to densification and volume changes at high temperatures. A $(La_{1-x}Y_x)_2Zr_2O_7$ sintered compound was prepared by the co-precipitation and oxalate methods, by adding lanthanum zirconate to yttria. The thermal properties and crystallinity obtained by the two different methods were compared. Both methods yielded pyrochlore structures, and the oxalate method confirmed phases at low temperatures. The thermal conductivity of the sintered bulk prepared by co-precipitation was 0.93 W/mK, while that prepared by the oxalate method was 0.85 W/mK. These values are superior to that of 4YSZ at $1,000^{\circ}C$, which is widely used in industries.

• 한국세라믹학회지
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• 제56권2호
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• pp.197-204
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• 2019

An electrochemical oxygen permeating membrane (OPM) is fabricated using Zr_0.895Sc_0.095Ce_0.005Gd_0.005O_2-δ (ScCeGdZ) as the solid electrolyte and aLa_0.7Sr_0.3MnO₃-bScCeGdZ composite (LZab, electrode) as the electrode. The crystal phase of the electrode and the microstructure of the membrane is investigated with X-ray diffraction and scanning electron microscopy. The electrochemical resistance of the membrane is examined using 2-p ac impedance spectroscopy, and LZ55 shows the lowest electrode resistance among LZ82, LZ55 and LZ37. The oxygen permeation is studied with an oxygen permeation cell with a zirconia oxygen sensor. The oxygen flux of the OPM with LZ55 is nearly consistent with the theoretical value calculated from Faraday's Law below a critical current. However, it becomes saturated above the critical current due to the limit of the oxygen ionic conduction of the OPM. The OPM with LZ55 has a very high oxygen permeation flux of ~ 3.5 × 10^-6 mol/㎠s in I = 1.4 A/㎠.

• 한국전기전자재료학회:학술대회논문집
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• 한국전기전자재료학회 2008년도 하계학술대회 논문집 Vol.9
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• pp.174-174
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• 2008

Non-volatile memories using ferroelectric-gate field-effect transistors (Fe-FETs) with a metal/ferroelectric/semiconductor gate stack (MFS-FETs) make non-destructive read operation possible. In addition, they also have features such as high switching speed, non-volatility, radiation tolerance, and high density. However, the interface reaction between ferroelectric materials and Si substrates, i.e. generation of mobile ions and short retention, make it difficult to obtain a good ferroelectric/Si interface in an MFS-FET's gate. To overcome these difficulties, Fe-FETs with a metal/ferroelectric/insulator/semiconductor gate stack (MFIS-FETs) have been proposed, where insulator as a buffer layer is inserted between ferroelectric materials and Si substrates. We prepared $SrBi_2Ta_2O_9$ (SBT) film as a ferroelectric layer and $LaZrO_x$ (LZO) film as a buffer layer on p-type (100) silicon wafer for making the MFIS-FET devices. For definition of source and drain region, phosphosilicate glass (PSG) thin film was used as a doping source of phosphorus (P). Ultimately, the n-channel ferroelectric-gate FET using the SBT/LZO/Si Structure is fabricated. To examine the ferroelectric effect of the fabricated Fe-FETs, drain current ($I_d$) versus gate voltage ($V_g$) characteristics in logarithmic scale was measured. Also, drain current ($I_d$) versus drain voltage ($V_d$) characteristics of the fabricated SBT/LZO/Si MFIS-FETs was measured according to the gate voltage variation.