• The Journal of Korean Institute of Communications and Information Sciences
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• v.30 no.1C
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• pp.61-72
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• 2005

For the improvement of coding efficiency, the H.264 standard uses new coding tools such as VBS, 1/4-pel accurate ME, multiple references, intra prediction, loop filter, etc. Using these coding tools, H.264 has achieved significant improvements from rate-distortion point of view compared to existing standards. However, the encoder complexity is greatly increased due to these coding tools. We focus on the complexity reduction method of MB mode selection. Among all modes which can be selected, $8{\times}8$ and intra $4{\times}4$ mode have higher complexity than the others. So we propose the methods for reduction of the $8{\times}8$ and intra $4{\times}4$ mode complexity by using information of other modes with relatively low complexity. Simulation results show that the proposed methods save up to $54.6{\%}$ of total encoding time while keeping the average decrease about 0.012dB in PSNR.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.44 no.1
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• pp.68-75
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• 2007

A single chip NFC transceiver supporting not only NFC active and passive mode but also 13.56MHz RFID reader and tag mode was designed and fabricated. The proposed NFC transceiver can operate as a RFID tag even without external power supply which has dual antenna structure for initiator and target. The area increment due to additional target antenna is negligible because the target antenna is constructed by using a shielding layer of initiator antenna. The analog front end circuit of the proposed NFC transceiver consists of a transmitter and receiver of reader/writer block supporting NFC initiator or RFID reader mode, and a tag circuit for target of passive NFC mode or RFID tag mode. The maximum baud rate of the proposed NFC device is 212kbps by using UART serial interface. The chip has been designed and fabricated using a Magnachip's $0.35{\mu}m$ double poly 4-metal CMOS process, and the effective area of the chip is 2200um by 3600um.

• Journal of the Institute of Electronics Engineers of Korea SP
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• v.43 no.3 s.309
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• pp.43-53
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• 2006

As wireless network technology has advanced, demands for multimedia contents through mobile environment have tendered to upward. Since network situation is changing every moment and types of user terminals are diverse, it is difficult for a content provider to consider network situation and type of user terminal to provide multimedia contents. As one solution, transcoding techniques have been proposed, but those have much complexity. In this paper, in order to reduce computational complexity, we propose a fast mode decision using input modes, motion vectors, and residual energies which are obtained from input bitstream for 2:1 down-scaling spatial transcoding application. The proposed method reduces processing time in mode decision by restricting possible mode types based on input information. Experimental results show that the proposed method achieves about 2.66 times improvement in encoding time compared to the normal encoding process while the PSNR is degraded by about 0.04dB, and bit-rate is increased by 1.6%.

• The KIPS Transactions:PartA
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• v.17A no.3
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• pp.121-126
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• 2010

This paper proposes a low-power MOS current-mode logic circuit with the low voltage swing technology and the high-threshold sleep-transistor. The sleep-transistor is used to high-threshold voltage PMOS transistor to minimize the leakage current. The $16{\times}16$ bit parallel multiplier is designed by the proposed circuit structure. Comparing with the conventional MOS current-model logic circuit, the circuit achieves the reduction of the power consumption in sleep mode by 1/104. The proposed circuit is achieved to reduce the power consumption by 11.7% and the power-delay-product by 15.1% compared with the conventional MOS current-model logic circuit in the normal mode. This circuit is designed with Samsung $0.18\;{\mu}m$ standard CMOS process. The validity and effectiveness are verified through the HSPICE simulation.

• The Journal of the Institute of Internet, Broadcasting and Communication
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• v.8 no.4
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• pp.89-95
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• 2008

In the maritime communication, Orthogonal Frequency Division Multiplexing (OFDM) communication terminal should be operated with low power consumption, because the communication should be accomplished in the circumstance of disaster. Therefore, Low power FFT processor is required to be designed with current mode signal processing technique than digital signal processing. Current- to-Voltage Converter (IVC) is a device that converts the output current signal of FFT processor into the voltage signal. In order to lessen the power consumption of OFDM terminal, IVC should be designed with low power design technique and IVC should have wide linear region for avoiding distortion of signal voltage. To design of one-chip of the FFT LSI and IVC, IVC should have a small chip size. In this paper, we proposed the new IVC with wide linear region. We confirmed that the proposed IVC operates linearly within 0.85V to 1.4V as a function of current-mode FFT output range of -100~100[uA]. Designed IVC will contribute to realization of low-power maritime data communication using OFDM system.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.35 no.11B
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• pp.1667-1675
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• 2010

This paper presents a high efficiency DC-DC buck converter for mobile device. The circuit employes simplified compensation circuit for its portability and for high efficiency at stand-by mode. This device operates at PFM mode when it enters stand-by mode(light load). In order to place the compensation circuit on chip, the capacitor multiplier method is employed, such that it can minimize the compensation block size of the error amplifier down to 30%. The measurement results show that the buck converter provides a peak efficiency of 93% on PWM mode, and 92.3% on PFM mode. The converter has been fabricated with a $0.35{\mu}m$ CMOS technology. The input voltage of the buck converter ranges from 2.5V to 3.3V and it generates the output of 3.3V.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.44 no.12
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• pp.25-30
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• 2007

In this paper, we proposed a new burst-mode optical transmitter structure which is suitable for high data rate operation such as Gb/s operation. With this structure we made a 1.25Gb/s burst-mode optical transmitter including a digitally controlled APC circuit for EPON systems using commercial 0.8m BiCMOS technology. It well functioned at 1.25Gb/s and showed good eye patterns with 53.3ps jitter, 191ps rise time and 258ps fall time. To characterize the APC function we measured optical output power as increasing external voltage VREF. The optical power is linearlyproportional to VREF at the rate of 0.293mW/V.

• Journal of Advanced Navigation Technology
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• v.14 no.1
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• pp.102-107
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• 2010

This paper presented a rate-distortion estimation method for effective mode decision in H.264/AVC. In this approach, in order to decide a mode, laplacian distribution modeling of DCT coefficients is utilized, which do not need to such process as quantization, entropy coding. From the simulation results, proposed a method showed that rate-distortion between proposed scheme and practical value was almost the same and performed 0.02dB of PSNR gain.

• Journal of the Korean Institute of Telematics and Electronics D
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• v.36D no.9
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• pp.50-55
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• 1999

In this paper we proposed a variable optical attenuator using the side polished fiber coupled with a refractive index matching liquid. Small variation of refractive index of matching liquid can induce very large change of optical loss due to the coupling between the fiber mode and radiation mode. The thermo-optic effect of matching liquid was used to ontrol the optical attenuation. The side polished fiber block was fabricated using the silicon V gloove. Experimental results showed that $5^{\circ}C$ temperature variation was enough to adjust full range attenuation. The polarization dependent loss and insertion loss of the fabricated devices were 0.5dB and 0.2dB respectively.

• Journal of Broadcast Engineering
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• v.10 no.3
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• pp.348-356
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• 2005

In this paper, we propose a fast bitrate reduction transcoding method to convert a bitstream coded by H.264 into a lower bitrate H.264 bitstream. Block mode informations and motion vectors generated by H.264 decoder are used for probability-based block mode determination in the proposed transcoding method. And the motion vector reuse and motion vector refinement process are applied in the proposed transcoding. In the experiment results, the proposed methods achieves approximately 40 times improvement in computation complexity compared with the cascaded pixel domain transcoding, while the PSNR(Peak Signal to Noise Ratio) is degraded with only $0.1\~0.3$ dB.