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http://dx.doi.org/10.4313/JKEM.2018.31.3.141

Improvement of Thermal Stability of Ni-InGaAs Using Pd Interlayer for n-InGaAs MOSFETs  

Li, Meng (Department of Electronics Engineering, Chungnam National University)
Shin, Geonho (Department of Electronics Engineering, Chungnam National University)
Lee, Jeongchan (Department of Electronics Engineering, Chungnam National University)
Oh, Jungwoo (Yonsei Institute of Convergence Technology, School of Integrated Technology, Yonsei University)
Lee, Hi-Deok (Department of Electronics Engineering, Chungnam National University)
Publication Information
Journal of the Korean Institute of Electrical and Electronic Material Engineers / v.31, no.3, 2018 , pp. 141-145 More about this Journal
Abstract
Ni-InGaAs shows promise as a self-aligned S/D (source/drain) alloy for n-InGaAs MOSFETs (metal-oxide-semiconductor field-effect transistors). However, limited thermal stability and instability of the microstructural morphology of Ni-InGaAs could limit the device performance. The in situ deposition of a Pd interlayer beneath the Ni layer was proposed as a strategy to improve the thermal stability of Ni-InGaAs. The Ni-InGaAs alloy layer prepared with the Pd interlayer showed better surface roughness and thermal stability after furnace annealing at $570^{\circ}C$ for 30 min, while the Ni-InGaAs without the Pd interlayer showed degradation above $500^{\circ}C$. The Pd/Ni/TiN structure offers a promising route to thermally immune Ni-InGaAs with applications in future n-InGaAs MOSFET technologies.
Keywords
MOSFET; Ni-InGaAs; $n-In_{0.53}Ga_{0.47}As$; Pd interlayer; Thermal stability;
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