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http://dx.doi.org/10.7471/ikeee.2018.22.2.420

An Accuracy Improvement Method for the Analysis of Process Variation Effect on CNTFET-based Circuit Performance  

Cho, Geunho (Dept. of Electronics Engineering, Seokyeong University)
Publication Information
Journal of IKEEE / v.22, no.2, 2018 , pp. 420-426 More about this Journal
Abstract
In the near future, CNTFET(Carbon NanoTube Field Effect Transistor) is considered as one of the most promising candidate for the replacement of modern silicon-based transistors by utilizing the ballistic or near-ballistic transport capability of CNT(Carbon NanoTube). For the large-scale fabrication of high performance CNTFET, semiconducting CNTs have to be well-aligned with a fixed pitch and high densities in the each CNTFET. However, due to the immaturity of the CNTFET fabrication process, CNTs can be unevenly positioned in a CNTFET and existing HSPICE library file cannot support the circuit level evaluation of performance variation caused by the unevenly positioned CNTs. To evaluate the performance variation, linear programming methodology was suggested previously, but the errors can be made during the calculation of the current and the gate capacitance of a CNTFET. In this paper, the reasons causing errors will be discussed in detail and the new methodology to reduce the errors will be also suggested. Simulation results shows that the errors can be reduced from 7.096% to 3.15%.
Keywords
CNTFET; CNT; Process Variation; Linear Prgramming; Defect Model;
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1 J. Deng, H.-S. P. Wong, "A Compact SPICE Model for Carbon-Nanotube Field-Effect Transistors Including Nonidealities and Its Application - Part I: Model of the Intrinsic Channel Region," IEEE Transactions on Electron Devices, vol 54, pp. 3186-3194, Nov. 2007.DOI: 10.1109/TED.2007.909030   DOI
2 J. Deng, H.-S. P.Wong, "A compact SPICE model for carbon nanotube field effect transistors including non-idealities and its application-Part II: Full device model and circuit performance benchmarking," IEEE Transactions on Electron Devices, vol. 54, pp. 3195-3205, Nov. 2007. DOI: 10.1109/TED.2007.909043   DOI
3 J. Deng and H. S. P. Wong, "Modeling and Analysis of Planar-Gate Electrostatic Capacitance of 1-D FET With Multiple Cylindrical Conducting Channels," IEEE Trans. Electron Devices, vol. 54, no. 9, pp. 23772385, 2007. DOI:10.1109/TED.2007.902047   DOI
4 H.-H. Byeon, W. C. Lee, W. Kim, S. K. Kim, W. Kim, and H. Yi, "Bio-fabrication of nanomesh channels of single-walled carbon nanotubes forlocally gated field-effect transistors," Nanotechnology, vol. 28, no. 2, p. 25304, Jan. 2017. DOI:10.1088/1361-6528/28/2/025304   DOI
5 N. Patil, J. Deng, A. Lin, H. S. P. Wong, and S. Mitra, "Design Methods for Misaligned and Mispositioned Carbon Nanotube Immune Circuits," IEEE Trans. Comput. Des. Integr. Circuits Syst., vol. 27, no. 10, pp. 1725-1736, 2008. DOI: 10.1109/TCAD.2008.2003278   DOI
6 G. Cho, F. Lombardi, and Y. B. Kim, "Modelling a CNTFET with Undeposited CNT Defects," in 2010 IEEE 25th International Symposium on Defect and Fault Tolerance in VLSI Systems, 2010, pp. 289-296. DOI: 10.1109/DFT.2010.4
7 J. Si et al., "Scalable Preparation of High Density Semiconducting Carbon Nanotube Arrays for High-Performance Field-Effect Transistors," ACS Nano, vol. 12, no. 1, pp. 627-634,Jan. 2018. DOI: 10.1021/acsnano.7b07665   DOI
8 G. Cho and F. Lombardi, "Circuit-Level Simulation of a CNTFET With Unevenly Positioned CNTs by Linear Programming," IEEE Trans. Device Mater. Reliab., vol. 14, no. 1, pp. 234-244, 2014. DOI: 10.1109/TDMR.2013.2279154   DOI